JPS6399485U - - Google Patents

Info

Publication number
JPS6399485U
JPS6399485U JP19368786U JP19368786U JPS6399485U JP S6399485 U JPS6399485 U JP S6399485U JP 19368786 U JP19368786 U JP 19368786U JP 19368786 U JP19368786 U JP 19368786U JP S6399485 U JPS6399485 U JP S6399485U
Authority
JP
Japan
Prior art keywords
transistors
electrode
electrodes
transistor
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19368786U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP19368786U priority Critical patent/JPS6399485U/ja
Publication of JPS6399485U publication Critical patent/JPS6399485U/ja
Pending legal-status Critical Current

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Landscapes

  • Processing Of Color Television Signals (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案に係るバースト信号及びクロ
マ信号の増幅回路の一実施例を示す回路構成図、
第2図は従来のバースト信号及びクロマ信号の増
幅回路を示す回路構成図である。 11…定電流源、12…差動増幅回路、13…
信号源、14…電源端子、15,16…端子、1
7…制御端子、18…出力端子、19,20…端
子、21〜23…定電流源。
FIG. 1 is a circuit configuration diagram showing an embodiment of the burst signal and chroma signal amplification circuit according to this invention;
FIG. 2 is a circuit diagram showing a conventional burst signal and chroma signal amplification circuit. 11...constant current source, 12...differential amplifier circuit, 13...
Signal source, 14...Power terminal, 15, 16...Terminal, 1
7... Control terminal, 18... Output terminal, 19, 20... Terminal, 21-23... Constant current source.

Claims (1)

【実用新案登録請求の範囲】 各エミツタ電極同志が共通接続された第1及び
第2のトランジスタを有し一方のトランジスタの
ベース電極にバースト信号とクロマ信号とを含む
カラーテレビジヨン信号が供給される差動増幅回
路と、 前記第1及び第2のトランジスタのいずれか一
方のコレクタ電極に各エミツタ電極が共に接続さ
れるとともに各ベース電極間に第1の利得制御用
電圧が供給される第3及び第4のトランジスタと
、 コレクタ電極が複数の電流制限素子を直列に介
して基準電位点に接続されるとともにエミツタ電
極が前記第3及び第4のトランジスタのエミツタ
電極に共通に接続される第5のトランジスタと、 前記第3及び第4のトランジスタのいずれか一
方のコレクタ電極に各エミツタ電極が共に接続さ
れるとともに各コレクタ電極が前記複数の電流制
限素子間の異なる接続点にそれぞれ接続され各ベ
ース電極間に第2の利得制御用電圧が供給される
第6及び第7のトランジスタと、 各エミツタ電極同志が共通に第1の定電流源に
接続され各ベース電極が前記第3及び第4のトラ
ンジスタのベース電極にそれぞれ接続されるとと
もに各コレクタ電極が前記第4及び第3のトラン
ジスタのコレクタ電極にそれぞれ接続される第8
及び第9のトランジスタと、 各エミツタ電極同志が共通に第2の定電流源に
接続され各ベース電極が前記第6及び第7のトラ
ンジスタのベース電極にそれぞれ接続されるとと
もに各コレクタ電極が前記第7及び第6のトラン
ジスタのコレクタ電極にそれぞれ接続される第1
0及び第11のトランジスタと、 コレクタ電極が前記複数の電流制限素子間の接
続点に接続されエミツタ電極が第3の定電流源に
接続された第12のトランジスタと、 各コレクタ電極同志が共通に前記基準電位点に
接続され各エミツタ電極が前記第8、第9のトラ
ンジスタのエミツタ電極共通接続点及び前記第1
0、第11のトランジスタのエミツタ電極共通接
続点にそれぞれ接続される第13及び第14のト
ランジスタと、 前記第5、第12乃至第14のトランジスタの
ベース電極にバースト信号期間に一致するゲート
信号を供給し前記バースト信号期間には前記第5
、第12乃至第14のトランジスタを導通させそ
れ以外の期間には前記第3、第4、第6、第7、
第8乃至第11のトランジスタを導通せしめる手
段とを具備し、 前記第5のトランジスタのコレクタ電極から前
記バースト信号及びクロマ信号の増幅出力を得る
ように構成してなることを特徴とするバースト信
号及びクロマ信号の増幅回路。
[Claims for Utility Model Registration] First and second transistors whose emitter electrodes are commonly connected are provided, and a color television signal including a burst signal and a chroma signal is supplied to the base electrode of one of the transistors. a differential amplifier circuit, and a third transistor whose emitter electrodes are both connected to the collector electrode of one of the first and second transistors, and a first gain control voltage is supplied between each base electrode. a fourth transistor; and a fifth transistor, the collector electrode of which is connected to a reference potential point via a plurality of current limiting elements in series, and the emitter electrode of which is commonly connected to the emitter electrodes of the third and fourth transistors. Each emitter electrode is connected to the collector electrode of one of the transistors, and each collector electrode is connected to a different connection point between the plurality of current limiting elements, and each base electrode is connected to the collector electrode of one of the third and fourth transistors. sixth and seventh transistors to which a second gain control voltage is supplied; and the third and fourth transistors whose emitter electrodes are commonly connected to the first constant current source and whose base electrodes are connected to the third and fourth transistors. an eighth transistor whose collector electrodes are respectively connected to the base electrodes of the fourth and third transistors;
and a ninth transistor, each emitter electrode is commonly connected to the second constant current source, each base electrode is connected to the base electrode of the sixth and seventh transistor, and each collector electrode is connected to the second constant current source. the first transistor connected to the collector electrodes of the seventh and sixth transistors, respectively;
a twelfth transistor whose collector electrode is connected to the connection point between the plurality of current limiting elements and whose emitter electrode is connected to a third constant current source, and whose collector electrodes are common to each other; Each emitter electrode is connected to the reference potential point and is connected to a common connection point between the emitter electrodes of the eighth and ninth transistors and the first
A gate signal corresponding to a burst signal period is applied to the base electrodes of the 13th and 14th transistors connected to the common connection point of the emitter electrodes of the 0 and 11th transistors, respectively, and the 5th, 12th to 14th transistors. and during the burst signal period, the fifth
, the 12th to 14th transistors are turned on, and the third, fourth, sixth, seventh,
and a means for making the eighth to eleventh transistors conductive, and configured to obtain amplified outputs of the burst signal and the chroma signal from the collector electrode of the fifth transistor; Chroma signal amplification circuit.
JP19368786U 1986-12-18 1986-12-18 Pending JPS6399485U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19368786U JPS6399485U (en) 1986-12-18 1986-12-18

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19368786U JPS6399485U (en) 1986-12-18 1986-12-18

Publications (1)

Publication Number Publication Date
JPS6399485U true JPS6399485U (en) 1988-06-28

Family

ID=31149942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19368786U Pending JPS6399485U (en) 1986-12-18 1986-12-18

Country Status (1)

Country Link
JP (1) JPS6399485U (en)

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