JPS641032A - Microcomputer circuit - Google Patents

Microcomputer circuit

Info

Publication number
JPS641032A
JPS641032A JP15550887A JP15550887A JPS641032A JP S641032 A JPS641032 A JP S641032A JP 15550887 A JP15550887 A JP 15550887A JP 15550887 A JP15550887 A JP 15550887A JP S641032 A JPS641032 A JP S641032A
Authority
JP
Japan
Prior art keywords
value
cpu
subroutine
circuit
executes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15550887A
Other languages
Japanese (ja)
Other versions
JPH011032A (en
Inventor
Noriyuki Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62-155508A priority Critical patent/JPH011032A/en
Priority claimed from JP62-155508A external-priority patent/JPH011032A/en
Publication of JPS641032A publication Critical patent/JPS641032A/en
Publication of JPH011032A publication Critical patent/JPH011032A/en
Pending legal-status Critical Current

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  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To read out a subroutine corresponding to a written value by writing the value, which corresponds to the subroutine to be read, in a register circuit before a call instruction.
CONSTITUTION: Lower and upper addresses of subroutines are arranged in subroutine lower and upper address ROMs 6 and 7. First, a CPU 1 writes the accumulator value in a register circuit 5 by an instruction OUT or the like. At this time, a call instruction control circuit 3 is started to start monitor of the instruction code which the CPU 1 executes, and the CPU 1 executes the program written in a program storage ROM 8. The circuit 3 detects that the CPU 1 reads in the instruction code of the call instruction, and the value designated by the circuit 5 is read out from the ROM, and the value similarly designated is read out from the ROM 7. The CPU 1 executes the subroutine corresponding to the value of the accumulator.
COPYRIGHT: (C)1989,JPO&Japio
JP62-155508A 1987-06-24 microcomputer circuit Pending JPH011032A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62-155508A JPH011032A (en) 1987-06-24 microcomputer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62-155508A JPH011032A (en) 1987-06-24 microcomputer circuit

Publications (2)

Publication Number Publication Date
JPS641032A true JPS641032A (en) 1989-01-05
JPH011032A JPH011032A (en) 1989-01-05

Family

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