JPH011032A - microcomputer circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] Field of Industrial Application] The present invention relates to a microcomputer circuit, and is capable of realizing the change of a read subroutine depending on conditions such as the value of an accumulator with a simple program. Regarding peripheral circuits of microcomputers.

[Prior Art] For example, an 8-bit microcomputer does not have an instruction to change the subroutine to be read depending on the condition of the accumulator value. The method shown in FIG. 4 or 5 was adopted.

Here, the method shown in FIG. 4 is a method in which the accumulator value is checked using a comparison instruction, and when a condition is matched, the corresponding subroutine is read out.

On the other hand, in the method shown in Figure 5, the jump destination address is written in the table, the jump destination address corresponding to the accumulator value is set in the programmable counter, the branch is made, and after the processing is completed, the return address is saved in memory in advance. This is the way to go back.

1. Problems to be Solved] In the conventional method described above, the method shown in FIG. 4 has a problem in that as the number of subroutines to be read increases, the average time required to read the subroutines increases.

On the other hand, with the method shown in Figure 5, branches can be made in a fixed amount of time regardless of the number of branches, but the software is complex, requires a large number of registers, and takes processing time. .

Therefore, the first object of the present invention is to solve the above-mentioned conventional problems, and even when it is desired to change the reading subroutine depending on the value of the accumulator, for example,
Easy? ) An object of the present invention is to provide a microcomputer circuit that can quickly process a program.

Solution to Problem 1] The present invention provides a subroutine upper address ROM and a subroutine lower address ROM in which addresses of subroutines to be read are arranged separately into upper addresses and lower addresses.
and the register circuit that specifies by writing the accumulator value from CI) the number of this arranged subroutine address to call, and the CPU
Detects that the instruction code of the all instruction has been read, and outputs a signal to select the subroutine lower address ROM in the first cycle of the following two memory read cycles, and the subroutine upper address ROM in the next cycle, A microcomputer circuit is constructed by providing a call command control circuit that deactivates the program ROM during this time.

[Example] Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block circuit diagram of a microcomputer circuit that is an embodiment of the present invention.

In the figure, 1 is a CP LJ, 2 is a cock circuit that oscillates the system clock, 3 is a call instruction control circuit, 4 is an address decoder, 5 is a register circuit,
6 is a subroutine lower address ROM, 7 is a subroutine upper address ROM, 8 is a program storage ROM,
9 is a path buffer, and 10 is a RAM.

In this embodiment, when a subroutine is read out according to the accumulator value as shown in FIG. 3, as shown in FIGS. The lower and upper addresses of subroutines are arranged.

First, the CPU writes an accumulator value into the register circuit 5 using an OUT command or the like. At this time, if the accumulator value is n, the output value of the register circuit 5 is n, which is the lower part of the subroutine.

For the upper address ROM 6.7, address n is designated. At this time, the call instruction control circuit 3 is activated and starts monitoring the instruction code executed by the CPU, while the CPU 1 executes the program stored in the program storage ROM 8.

Here, call the subroutines CallX and Y3.
A case where a byte instruction is stored in the program storage ROM 8 will be explained.

In the conventional technology, the CPU 1 reads the program storage ROM 8 in the following order: 1) the instruction code of the Call instruction, 2) the lower address of the subroutine (here, the Y address), and 2) the higher address of the subroutine (here, the X address), and
.

I was doing Y.

In the device of this embodiment, the Call instruction control circuit 3 detects that the CPU 1 has read the instruction code of the Call instruction in the cycle (2), and makes the YO output active in the cycle (2). As a result, the subroutine lower address ROM 6 and the pass buffer 9 become active, and the program storage ROM 8 becomes inactive.

From the subroutine lower address ROM 6, the value N2 at address n specified by the register circuit 5 is output onto the data bus via the path buffer 9, and is sent to C))U.
l will be read.

In the next cycle (2), the Call instruction control circuit 3 activates the Y1 output.

As a result, the subroutine upper address ROM 7 and the pass buffer 9 become active, and the t7gram storage flO
M8 becomes inactive, and as in the case of ■, the value N1 at address n of the subroutine upper address ROM7 is changed to C)).
U1 will read it.

As mentioned above, in the cycles ■ and ■, the program storage I
Since t OM 8 is prohibited and X and Y are not actually output onto the data bus, no data breaks occur. As a result, CI) Ul executes subroutines Nl and N2 corresponding to the value n of the accumulator.

Here, when comparing this embodiment with the conventional technology, the device of this embodiment can realize the flowchart shown in FIG. 3 with only two instructions, the OU 'r' instruction and the Call instruction.
27 states in a cycle (OUT...10 states,
Call...17 states).

On the other hand, in the case of Fig. 4, the ratio axis command, Ca11
Assuming that you repeat the command and compare n times,
7・n-1-10(n-1) -1-27 sdate is necessary (comparison... 7 sdate, if not match proceed to next comparison...10 states, if match jump 7
ICall...27 states), as n increases, the number of states also increases significantly. On the other hand, in the case of Figure 5, 81
State is required.

As described above, according to this embodiment, the processing can be easily executed and the processing time can be significantly reduced.

Note that the present invention is not limited to the above embodiments,
Various modifications are possible within the scope of the invention.

[Effects of the Invention] As described above, according to the present invention, a subroutine corresponding to the subroutine to be read can be read by simply writing a value corresponding to the subroutine to be read into the register circuit before the Cal+ instruction.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram of a device according to an embodiment of the present invention, and FIG.
Figures (A> and (B) are schematic explanatory diagrams showing examples of the contents of the subroutine upper address ROM and the subroutine lower address ROM, respectively. Figure 3 is a flowchart when reading the subroutine corresponding to the accumulator value.
5 are flowcharts showing detailed conventional procedures for realizing the flowchart of FIG. 3. 1: CPU, 3: Call instruction control circuit, 5: Register circuit, 6: Subroutine lower address ROM, 7: Subroutine upper address ROM, 8: Program ROM. Agent Patent Attorney Kihei Watanabe Figure 1 Figure 2 (Al (81 Figure 3)

Claims (1)

[Claims] A CPU, a program ROM that stores programs to be executed by the CPU, a register circuit in which the location of the subroutine address from the CPU in the subroutine address ROM is written; connected to the arranged subroutine upper address ROM and the register circuit,
The CPU detects that the lower address ROM in which the lower addresses of the subroutine are arranged and the instruction code of the Call instruction is read, and the subroutine lower address ROM is read in the first cycle of the following two memory read cycles. A microcomputer circuit comprising: a call instruction control circuit which outputs a signal for selecting a subroutine upper address ROM in the next cycle and makes the program ROM inactive.