JPS6410351A - Information collection processing system - Google Patents

Information collection processing system

Info

Publication number
JPS6410351A
JPS6410351A JP62166705A JP16670587A JPS6410351A JP S6410351 A JPS6410351 A JP S6410351A JP 62166705 A JP62166705 A JP 62166705A JP 16670587 A JP16670587 A JP 16670587A JP S6410351 A JPS6410351 A JP S6410351A
Authority
JP
Japan
Prior art keywords
information
circuit
processor
interruption
microprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62166705A
Other languages
Japanese (ja)
Inventor
Tetsuo Kudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62166705A priority Critical patent/JPS6410351A/en
Publication of JPS6410351A publication Critical patent/JPS6410351A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To collect information without affecting hardware by informing the information collection timing and its information to a processor and interrupting the operation so far carried out by the processor to collect the information designated by the processor itself. CONSTITUTION:A trigger factor including an address indicating the coincidence of address conditions is given to an interruption generating circuit 400. Under such conditions, a microprocessor 10 carries out the prescribed processing and the circuit 400 gives an interruption to the processor 10 when the conditions corresponding to the trigger factor are produced. The microprocessor 10 works in an information collection routine called by an interruption processing routine and loads the information stored in a register group 200 into an information exchange circuit 500 based on the address set to the circuit 500. Then the microprocessor 10 is reset to its state set before interruption. The circuit 500 transfers the received information to an external device.
JP62166705A 1987-07-03 1987-07-03 Information collection processing system Pending JPS6410351A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62166705A JPS6410351A (en) 1987-07-03 1987-07-03 Information collection processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62166705A JPS6410351A (en) 1987-07-03 1987-07-03 Information collection processing system

Publications (1)

Publication Number Publication Date
JPS6410351A true JPS6410351A (en) 1989-01-13

Family

ID=15836231

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62166705A Pending JPS6410351A (en) 1987-07-03 1987-07-03 Information collection processing system

Country Status (1)

Country Link
JP (1) JPS6410351A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03204737A (en) * 1990-01-08 1991-09-06 Nec Corp Debug circuit of signal processing processor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5971556A (en) * 1982-10-18 1984-04-23 Nec Corp Data collection system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5971556A (en) * 1982-10-18 1984-04-23 Nec Corp Data collection system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03204737A (en) * 1990-01-08 1991-09-06 Nec Corp Debug circuit of signal processing processor

Similar Documents

Publication Publication Date Title
JPS5549729A (en) Data transfer system
JPS53145536A (en) Interruption process system
JPS54949A (en) Information retrieval unit
JPS5619593A (en) Parity check processing system for memory
JPS5347737A (en) Detection circuit for process request
JPS5440049A (en) Information process system
JPS55150071A (en) Card reader
JPS546732A (en) Matching debug device for pattern recognizing device
JPS5515565A (en) Data collection system
JPS5696331A (en) Panel function control system
JPS5420625A (en) Fault discrimination ststem of memory system
JPS5693455A (en) Line monitor system
JPS5417636A (en) Address-over detection system of memory unit
JPS5356936A (en) Transfer control system
JPS5361938A (en) Automatic diagnosis device
JPS553011A (en) Error processing system for sequence control unit
JPS57109058A (en) Step system of microcomputer
JPS5533239A (en) Interruption processing system
JPS5561858A (en) Central operation control unit
JPS5543687A (en) Process system at fault time of power source
JPS54137939A (en) Interruption system by number of assigned steps
JPS55135949A (en) Soft test support device of microcontroller
JPS5552161A (en) Information processing system
JPS57152056A (en) Detection system for hardware failure
JPS53148354A (en) Detection system for name coincidence