JPS641045A - Buffer memory circuit device - Google Patents

Buffer memory circuit device

Info

Publication number
JPS641045A
JPS641045A JP63024926A JP2492688A JPS641045A JP S641045 A JPS641045 A JP S641045A JP 63024926 A JP63024926 A JP 63024926A JP 2492688 A JP2492688 A JP 2492688A JP S641045 A JPS641045 A JP S641045A
Authority
JP
Japan
Prior art keywords
signal
request
buffer memory
memory
mrd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63024926A
Other languages
Japanese (ja)
Other versions
JPH011045A (en
Inventor
Koji Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63024926A priority Critical patent/JPS641045A/en
Publication of JPH011045A publication Critical patent/JPH011045A/en
Publication of JPS641045A publication Critical patent/JPS641045A/en
Pending legal-status Critical Current

Links

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To delay the next request in case of a write interval to process the request after the delay time by coupling a buffer memory circuit to a request source and receiving the next address during block transfer and processing the next received request unless the buffer memory is in the write interval.
CONSTITUTION: A buffer memory circuit device 10 is connected between a request source 11 and a main storage 13, and a request signal RQ is continuously supplied to the device 10 from the request source 11. The device 10 generates a memory request signal NRQ and a memory address signal MAD in relation to the signal RQ and an address signal AD and sends them to the storage 12. The storage 12 supplies continuous memory reply data unit signal MRD and memory rely signal MRP to the device 10 in response to these signals NRQ and MAD respectively. The signal MRD executes block transfer, and blocks are continuously sent from the device 12 to the device 10, and execution is transferred from the first signal MRD to the last if there are no blocks in the device 10.
COPYRIGHT: (C)1989,JPO&Japio
JP63024926A 1987-02-07 1988-02-06 Buffer memory circuit device Pending JPS641045A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63024926A JPS641045A (en) 1987-02-07 1988-02-06 Buffer memory circuit device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2557487 1987-02-07
JP62-25576 1987-02-07
JP62-25574 1987-02-07
JP63024926A JPS641045A (en) 1987-02-07 1988-02-06 Buffer memory circuit device

Publications (2)

Publication Number Publication Date
JPH011045A JPH011045A (en) 1989-01-05
JPS641045A true JPS641045A (en) 1989-01-05

Family

ID=26362508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63024926A Pending JPS641045A (en) 1987-02-07 1988-02-06 Buffer memory circuit device

Country Status (1)

Country Link
JP (1) JPS641045A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61228540A (en) * 1985-04-01 1986-10-11 Nec Corp Cache memory control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61228540A (en) * 1985-04-01 1986-10-11 Nec Corp Cache memory control system

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