JPS641048A - Process priority level control system - Google Patents

Process priority level control system

Info

Publication number
JPS641048A
JPS641048A JP2443388A JP2443388A JPS641048A JP S641048 A JPS641048 A JP S641048A JP 2443388 A JP2443388 A JP 2443388A JP 2443388 A JP2443388 A JP 2443388A JP S641048 A JPS641048 A JP S641048A
Authority
JP
Japan
Prior art keywords
priority level
processors
stored
processor
control system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2443388A
Other languages
Japanese (ja)
Other versions
JPH011048A (en
Inventor
Yasushi Yokoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2443388A priority Critical patent/JPS641048A/en
Publication of JPH011048A publication Critical patent/JPH011048A/en
Publication of JPS641048A publication Critical patent/JPS641048A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4818—Priority circuits therefor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To reduce the overhead loss due to process switching by reporting decision results from a priority level deciding means to a pertinent processor and performing process swapping by this processor to make it unnecessary for the processor, which newly originates a process, to judge the swap object. CONSTITUTION:A process priority level control system consists of a system controller 200 and plural processors 100-103, and registers 50-53 in which a priority level CPRI of execution in the controller 200 is stored are connected to each of processors 100-103 by lines 60-63. A selecting circuit 20 is connected to processors 100-103, and a priority level of the process which at least one of processors 100-103 originates is selected by the circuit 20 and the selection result is stored in a register 10. Processors which execute processes having priority levels lower than the priority level NPRI are selected by a priority level discriminating circuit 30 in accordance with priority levels NPRI and CPRI stored in the register 10 and 50-53 and are reported to respective processors.
JP2443388A 1987-02-07 1988-02-03 Process priority level control system Pending JPS641048A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2443388A JPS641048A (en) 1987-02-07 1988-02-03 Process priority level control system

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2557187 1987-02-07
JP62-25571 1987-02-07
JP2443388A JPS641048A (en) 1987-02-07 1988-02-03 Process priority level control system

Publications (2)

Publication Number Publication Date
JPH011048A JPH011048A (en) 1989-01-05
JPS641048A true JPS641048A (en) 1989-01-05

Family

ID=26361936

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2443388A Pending JPS641048A (en) 1987-02-07 1988-02-03 Process priority level control system

Country Status (1)

Country Link
JP (1) JPS641048A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03253025A (en) * 1990-03-02 1991-11-12 Nippon Telegr & Teleph Corp <Ntt> Substrate to be worked and anisotropic etching of silicon

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5697169A (en) * 1979-12-29 1981-08-05 Fujitsu Ltd Multidata processing system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5697169A (en) * 1979-12-29 1981-08-05 Fujitsu Ltd Multidata processing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03253025A (en) * 1990-03-02 1991-11-12 Nippon Telegr & Teleph Corp <Ntt> Substrate to be worked and anisotropic etching of silicon

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