JPH011048A - Process priority control system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a process priority control system in a multiprocessor type data processing device having multiple programming control functions.

[Conventional technology]

Multiprogramming control includes program switching processing to efficiently execute a wide variety of processing in parallel. This multiple programming control function is an important basic control function for improving computer performance. A process is a unit of control on hardware when such multiprogramming control is realized as a function of a central processing unit. A process with a high priority given to each process is selected from among a plurality of executable processes as a process to be executed on the central processing unit. For example, while a running process waits for an I/O operation to complete in response to an I/O request by a running process, the running process is placed in a waiting state and Give up the central processing unit as a hardware resource to another process.

In addition, when the process in the standby state becomes executable in response to the completion of the dispatch operation, the priority of the currently executing process and the priority of the newly executable process are compared, and if necessary, In this case, the running processes are replaced.

In this way, when a running process enters a standby state and hands over the central processing unit to another executable process,
When a new process is added to the queue of executable processes, the priorities assigned to each process are compared, and competition control is performed to determine which process to execute.

2. Description of the Related Art In recent years, in order to meet the demand for a significant improvement in processing power, data processing devices (hereinafter referred to as multiprocessor systems) in which a number of central processing units (hereinafter referred to as processors) are tightly coupled have been developed. In such a multiprocessor system, a process corresponding to each processor is extracted from a matrix of executable processes and put into an execution state. Therefore, as many processes as there are processors are executed in parallel.

When a new executable process is created in this multiprocessor system, the priority assigned to each of the multiple processes running on each processor (hereinafter referred to as current priority CPRI) and the new executable process are A comparison is made with the priority given to the given process (hereinafter referred to as new priority NPRI).

As a result, if there is a current priority CPRI lower than the new priority NPRI, the running process, which is the process with the lowest current priority CPRI among these lower current priorities, is replaced with the process of NPR4 (hereinafter referred to as process - An instruction is given (referred to as a swap). If there is no current priority CPRI lower than the new priority NPRI, all processors continue executing the running processes.

[Problem to be solved]

In a conventional multiprocessor system having multiple programming control functions, priorities given to processes running on each processor are stored in a main memory space that can be referenced by each processor. The processor that spawned a new executable process compares the priority corresponding to that process with the priority stored in the main memory space, selects the processor that requires process swapping, and selects the processor through the interprocessor communication means. sends a process swap request to the specified processor.

However, such a priority comparison operation causes an overhead loss related to main memory access, resulting in a disadvantage that the system throughput is reduced.

Furthermore, if this priority comparison operation is performed by the processor that spawned the process, each processor must be equipped with a hardware configuration for the same comparison logic,
As a result, there is a drawback that the amount of hardware in the entire multiprocessor system increases.

An object of the present invention is to provide a process priority control system that reduces overhead loss during process switching and improves system throughput.

[Means to solve the problem]

A process priority control system in a multiprocessor system according to one aspect of the present invention includes a first storage means for storing priorities of processes being executed on a processor in the multiprocessor system, and a process priority for a newly executable process. and a second storage means for storing a priority of the newly executable process using the priorities stored in the first and second storage means. a priority determining means for selecting a processor currently executing the process; a notifying means for notifying the corresponding processor of the determination result of the determining means; and executing a process currently being executed on the corresponding processor in response to the notification from the notifying means. In addition to the matrix of possible processes, it also includes an execution process switching means for putting the newly executable process into an execution state.

〔Example〕

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

Referring to FIG. 1, one embodiment of the present invention includes a plurality of processors #0 100, for example four. Processor #1 10
1. Processor #2 102. ” and processor $3
103 and a system control device 200.

The system control device 200 has a register 50.0 that stores the priority level CPRI#0 of the process being executed on the processor #0100. A register 51 that stores the priority CPRI #1 of the process being executed on the processor #1101. Priority CPR of process running on processor #2102
Register 52 for storing I#2. Processor #3103
A register 53. stores the priority level CPRI#3 of the process currently being executed. A selection circuit 20 that selects the priority NPRI of a newly spawned process in at least one of the processors #0-$3100-103. A register 10 receives and stores the selection result of this selection circuit 20 via a line 21.
．． Priority NPRI is given from this register 10 via line 11 and from these registers 50-53 via line 4.
Priority given via 0-43 CPRI#O-#
A priority determination circuit 30.3 selects a processor that is executing a process with a priority lower than priority NPRI using priority NPRI. And lines 70-73 are provided for transmitting signals for notifying the corresponding processors 100-103 of the determination result of the priority determination circuit 30.

Each of the four processors #O-#3 100-103 is 1. Execution process switching means 110 for adding a process currently being executed by a corresponding processor to a matrix of executable processes in response to a signal applied through lines 70 to 73, and placing the newly executable process in an execution state; 111
, 112 and 113.

Note that each of the processors #0 to #3 and 100 to 103 is connected to a shared main memory (not shown).

Next, the operation of one embodiment of the present invention will be described in detail.

In a multiprocessor system having multiple programming control functions, each processor can take out a process one by one from a queue of only one executable process in the system and put it into an execution state. Each processor stores the contents of the instruction counter, general-purpose registers, address space registers, condition codes, and other software-visible registers (not shown) of the process to be executed in main memory (not shown) unique to the process. The instruction is transferred from the save area to the processor and starts executing the instruction. At the start of instruction execution, each processor stores the priority of this process in registers 50-53 corresponding to the executing processor. Note that the lowest priority as the initial value or the priority of a processor that is not executing a process is register 10. and stored in 50-53. Therefore, priority control is performed using the same logic even for idle processors.

Currently, all four processors #0-#3 100-103 are executing processes, and processor #3103
In response to the generation of a new process in the signal line 632 selection circuit 20., the priority NPRI of the process is determined. and is stored in the register 10 via the signal line 21. moreover,
In response to this store signal (not shown), register 10. and 50-53 to line 11. and priorities NPRI, CPRI#O, CPRI#1 . C.P.
RI#2. and CPRI#3 are output. Based on these priorities, the priority order determination circuit 30 makes the following determination.

Referring to FIG. 1, FIG. 2A, FIG. 2B, FIG. 2C, and FIG. 2D, the priority determination circuit 3'0 has a priority C
The lowest priority is selected from PRI#O-#3 (steps 301, 305, 309 and 313). It is then determined whether the selected lowest priority is lower than priority NPRI (steps 302, 306, 310. and 314).

If the selected lowest priority among priorities CPRI#O-#3 is lower than priority NPR, step 3 (
12, 306, 310 and 314, the corresponding processor #0-93. A process swap request signal with a logical value of "1" is sent to the line 70-73 connected to one of the lines 100-103 (steps 303, 307, 31).
1 and 315). If it is determined in steps 301, 305, 309 and 313 that the corresponding priority is not the lowest, or in these steps 301, 305, 309
If it is determined in step 313 that the priority selected as the lowest priority is higher than priority NPRI, the signal on the corresponding line 70-73 becomes a logical value "0" (steps 304, 308, 312 and 316). ). In the priority control in this embodiment, there is only one register 10, and the contents of registers 50 to 53 can be independently rewritten by each processor. Therefore, in order to ensure that rewriting of the registers by other processors is prohibited, lock control is performed between the processor and the assigner when setting values to these registers and setting the processor swap request signal.

In response to the determination result provided from this priority determination circuit 30 via lines 70-73, processors #O-#3, 1
Execution process switching means 111-113 in 00-103
operates as follows.

Referring to FIGS. 1 and 3, the dispatcher 400 of the execution process switching means 110-113
In response to the logic "I I+" of the signal on 0-73, it is determined whether or not the own processor is free (step 401). It is determined whether the queue is empty (step 402). In response to the determination that the queue is not empty in step 402, it is determined whether there is a runnable process (step 403).
). In response to the determination of the existence of a runnable process in step 403, the process with the highest priority in the queue of runnable processes rolls? (Step 4
04). After this, the processor free display bit (not shown) becomes "0" (step 405). Note that even if the queue of executable processes is empty or not empty, the process that can run on its own processor If the event does not exist, the system enters an idle state, and if an event occurs, system event processing is performed in response to the event (step 406).

In response to the determination that the own processor is not free in step 406, the process mode is entered (step 407).
).

Thereafter, it is determined whether there is a process that can run on the own processor (step 408).

In response to the determination of the existence of a runnable process in step 408, the highest priority process among the runnable processes is extracted (step 409). Next, it is determined whether the priority NPRI of the newly spawned process is higher than the priority CPRI of the currently executing process (step 410). In response to the determination in step 410 that the priority NPRI is higher than the priority CPRI, the currently executing process is swapped with the newly spawned process (step 411).

After this swap operation is completed, the instruction following the newly rolled-in instruction is executed (step 412).

In this way, each of the execution process switching means 110-113 adds the process currently being executed by the corresponding processor to the execution process matrix in response to the process swap request signal, and puts the newly executable process into the execution state. shall be.

Note that if it is determined in step 408 that there is no process that can run on the currently executing processor, or if it is determined in step 410 that the priority level N of the newly created process is
If it is determined that the PRI is equal to or lower than the priority of the currently executing process, the next instruction of the currently executing, suspended process is executed (step 412).

〔Effect of the invention〕

In a multiprocessor system, the system of the present invention uses a register that stores the priority of a process currently being executed on each processor and a priority of a process that has become newly executable, and the priority stored in this register. and priority determining means for specifying a processor to which process swapping is to be performed. The present invention notifies the relevant processor of the determination result from this priority determination means, and the relevant processor performs a process swap, thereby eliminating the need for the processor that has spawned a new process to determine the processor to be swapped. This has the effect of reducing overhead loss during process switching and improving system throughput.

[Brief explanation of the drawing]

1 is a diagram showing an embodiment of the present invention; FIGS. 2A to 2D are flowcharts showing the logic of the priority determination circuit 30 of FIG. 1; and FIG. 3 is an execution process switching means of FIG. 1. 110°111.112 and 11
3 is a diagram showing an example of the configuration of No. 3. FIG. In the figure, 100, 101, 102 and 103...processor, 200...system control device, 10,
50°51.52 and 53...Register, 2
0...Selection circuit, 30...Priority determination circuit. Agent: Patent Attorney Shinsuke Uchihara/ZAIm Kasumichi/B Zuken/C Zuo 3

Claims (1)

[Scope of Claims] First storage means for storing the priorities of processes being executed by processors in a multiprocessor system; second storage means for storing the priorities of processes that have become newly executable; priority determination means for selecting a processor that is executing a process with a lower priority than the priority of the newly executable process, using the priorities stored in the first and second storage means; , notification means for notifying the determination result of the determination means to the relevant processor; and in response to the notification from the notification means, adding the process currently being executed on the relevant processor to the matrix of executable processes, and adding the process to the newly executable process matrix. 1. A process priority control system comprising: executable process switching means for placing a process in an execution state.