JPS6410672U

JPS6410672U -

Info

Publication number: JPS6410672U
Application number: JP10539487U
Authority: JP
Priority date: 1987-07-10
Filing date: 1987-07-10
Publication date: 1989-01-20

Description

[Brief explanation of the drawing]

第１図は本考案の基本的構成図、第２図は第１
図のバス入出力切替回路の実施例の構成図、第３
Ａ図は第２図において切替制御信号ＢＴが“Ｌ”
のときの等価回路図、そして、第３Ｂ図は第２図
において切替制御信号ＢＴが“Ｈ”のときの等価
回路図である。符号の説明、１_１，…１ｉ，…１ｎ……システ
ム、２……バス、３……ドライバ、４……レシー
バ、５ａ，５ｂ，５ｃ，７ａ，７ｂ，８……信号
線、６ａ，６ｂ，６ｃ，９ａ，９ｂ，９ｃ……ス
イツチング用ＦＥＴ、１０_１，…１０ｉ，…１０
ｎ……バス入出力切替回路、１１，１２……イン
バータ、２０……切替制御信号発生部、３０……
テスト信号送信・検出部、４０……バス入出力制
御部。 Figure 1 is the basic configuration diagram of the present invention, Figure 2 is the basic configuration diagram of the present invention.
A configuration diagram of an embodiment of the bus input/output switching circuit shown in Figure 3.
In Figure A, the switching control signal BT is "L" in Figure 2.
FIG. 3B is an equivalent circuit diagram when the switching control signal BT is "H" in FIG. 2. Explanation of symbols, 1 ₁ ,...1i,...1n...System, 2...Bus, 3...Driver, 4...Receiver, 5a, 5b, 5c, 7a, 7b, 8...Signal line, 6a, 6b , 6c, 9a, 9b, 9c... Switching FET, 10 ₁ ,... 10i,... 10
n... Bus input/output switching circuit, 11, 12... Inverter, 20... Switching control signal generation unit, 30...
Test signal transmission/detection section, 40...bus input/output control section.

Claims

[Claims for Utility Model Registration] 1 System 1 for inputting and outputting signals to bus 2
₁ ,...1i,...1n, the bus input/output switching circuits ₁₀₁ ,...10i,...10n, the switching control signal generation section 20, the test signal transmission/detection section 30, and the bus input/output control section 40, and the switching control signal generating section 20 generates a switching control signal S
W, and the test signal transmission/detection section 30 connects to the bus 2.
Send a test signal to one end of the test target section,
and detects the test signal from the other end of the test target section, and the bus input/output control unit 40 controls input of the test signal to the bus 2 at the one end of the test target section and from the other end. transmits a bus input/output control signal for controlling the output of the test signal from the bus 2 in the bus input/output switching circuits 10 ₁ , . . . 10i, .
10n, each 10i is the attached system 1
i has a first configuration for inputting and outputting signals to and from the bus 2, and a second configuration for inputting and outputting the test signal to and from the bus 2 under control of the bus input/output control signal, A bus test device characterized in that, in accordance with the switching control signal SW, only one of the first configuration or the second configuration is brought into a conductive state and the other is brought into a disconnected state. 2 The bus input/output switching circuit 10 ₁ ,...10i,
...10n, each 10i is a driver 3 that outputs a signal to the bus 2.
and a receiver 4 that inputs the signal on the bus 2; and a system 1i including the respective bus input/output switching circuits 10i, which connects the driver 3 and the receiver 4.
a first signal line group 5a, 5b, 5c used only when using the driver 3 and the first signal line group 5a, 5b, 5c by the switching control signal SW; a first connected to the receiver 4 or disconnected from the driver 3 and the receiver 4;
a second group of signal lines 7 for applying the input/output control signals to the driver 3 and the receiver 4;
a, 7b, and applying the test signal to the driver 3 and transmitting the signal from the receiver 4 to the test signal transmitter.
a third signal line 8 for leading to the detection section 30; and a third signal line group 7a, 7b, 8 for guiding the second and third signal line groups 7a, 7b, 8 to the driver 3 in accordance with the switching control signal SW.
and the receiver 4, or
A bus test device according to claim 1, which comprises a second group of switches 9a, 9b, 9c that are disconnected from the driver 3 and the receiver 4.