JPS6410833U

JPS6410833U -

Info

Publication number: JPS6410833U
Application number: JP10538387U
Authority: JP
Priority date: 1987-07-10
Filing date: 1987-07-10
Publication date: 1989-01-20
Anticipated expiration: 2002-07-10
Also published as: JPH0726754Y2

Description

[Brief explanation of the drawing]

第１図はこの考案の機能ブロツク図、第２図は
この考案を適用したワードプロセツサの基本的な
構成を示すブロツク回路図である。１１……キーボード、１２−１……キーデコー
ダ、１２−２……キーバツフア、１２−３……転
送データ作成部、１３−２……検出部、１３−３
……入力バツフア、１３−５……本体ＣＰＵ。 FIG. 1 is a functional block diagram of this invention, and FIG. 2 is a block circuit diagram showing the basic configuration of a word processor to which this invention is applied. 11...Keyboard, 12-1...Key decoder, 12-2...Key buffer, 12-3...Transfer data creation section, 13-2...Detection section, 13-3
...Input buffer, 13-5...Main CPU.

Claims

[Claims for Utility Model Registration] A key buffer that sequentially stores input key data is provided, and the key data stored in the key buffer is read out in response to a data transfer request to perform input processing according to the key data. The input processing device includes: a determining means for determining the operation of a specific key; and an input for adding specific information to the key data stored at the beginning of the key buffer when the determining means determines that the specific key has been operated. a control means; a detection means for detecting whether or not the specific information is added to the key data transferred from the key buffer; and when the detection means detects that the specific information is added; A processing control device comprising: specific processing execution means for executing processing according to specific information;