JPS641229A - Formation of iii-v semiconductor conductive layer - Google Patents

Formation of iii-v semiconductor conductive layer

Info

Publication number
JPS641229A
JPS641229A JP15690387A JP15690387A JPS641229A JP S641229 A JPS641229 A JP S641229A JP 15690387 A JP15690387 A JP 15690387A JP 15690387 A JP15690387 A JP 15690387A JP S641229 A JPS641229 A JP S641229A
Authority
JP
Japan
Prior art keywords
substrate
ion implanted
iii
ions
prepared
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15690387A
Other languages
Japanese (ja)
Other versions
JPH011229A (en
Inventor
Michihisa Kono
Masaaki Kuzuhara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15690387A priority Critical patent/JPS641229A/en
Publication of JPH011229A publication Critical patent/JPH011229A/en
Publication of JPS641229A publication Critical patent/JPS641229A/en
Pending legal-status Critical Current

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  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE: To effectively suppress the warpage of a substrate and the generation of a slip line on the basis of irregular heat in the substrate by interposing a III-V single crystal substrate to which ions ere implanted at a predetermined position between upper and lower quartz glasses, and annealing it in a short time.
CONSTITUTION: A GaAs substrate 1 so prepared as to be first manufactured as an undoped substrate of plane orientation <100> by an LEC (Liquid Encapsulated Czochralski) method and then to be so ion implanted at room temperature to have 5× 1012/cm of concentration, for example, with 100keV of implanting energy of ions 29Si+ at a predetermined position is prepared. Then, the ion implanted substrate 1 is interposed between upper and lower quartz glass plates 6 to be contained in a quartz glass furnace tube 4, and annealed, for example, at 950°C for 5sec. by a halogen lamp 5. In this case, the ion implanted surface may be directed upward or downward.
COPYRIGHT: (C)1989,JPO&Japio
JP15690387A 1987-06-23 1987-06-23 Formation of iii-v semiconductor conductive layer Pending JPS641229A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15690387A JPS641229A (en) 1987-06-23 1987-06-23 Formation of iii-v semiconductor conductive layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15690387A JPS641229A (en) 1987-06-23 1987-06-23 Formation of iii-v semiconductor conductive layer

Publications (2)

Publication Number Publication Date
JPH011229A JPH011229A (en) 1989-01-05
JPS641229A true JPS641229A (en) 1989-01-05

Family

ID=15637917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15690387A Pending JPS641229A (en) 1987-06-23 1987-06-23 Formation of iii-v semiconductor conductive layer

Country Status (1)

Country Link
JP (1) JPS641229A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60239400A (en) * 1984-05-11 1985-11-28 Sumitomo Electric Ind Ltd Annealing method for compound semiconductors

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60239400A (en) * 1984-05-11 1985-11-28 Sumitomo Electric Ind Ltd Annealing method for compound semiconductors

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