JPS6412640A - Monitor system for time switching circuit - Google Patents

Monitor system for time switching circuit

Info

Publication number
JPS6412640A
JPS6412640A JP62168261A JP16826187A JPS6412640A JP S6412640 A JPS6412640 A JP S6412640A JP 62168261 A JP62168261 A JP 62168261A JP 16826187 A JP16826187 A JP 16826187A JP S6412640 A JPS6412640 A JP S6412640A
Authority
JP
Japan
Prior art keywords
signal
monitor signal
switching circuit
time slot
time switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62168261A
Other languages
Japanese (ja)
Inventor
Hiroyuki Oide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62168261A priority Critical patent/JPS6412640A/en
Publication of JPS6412640A publication Critical patent/JPS6412640A/en
Pending legal-status Critical Current

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  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To detect a processing error in addition to the line interruption in a time switching circuit by inserting a supervisory signal with a prescribed pattern in the unit of bits constituting an idle time slot. CONSTITUTION:A monitor signal inserting means 10 inserting a monitor signal (3) moitoring a bit pattern to an idle time slot while deviating the signal for each line and a time switching means 20 replacing the content between time slots with a data inserted thereto are provided. Moreover, a monitor signal error detection means 30 detecting a processing error or missing of processing in the monitor signal (3) depending on the bit pattern of the idle time slot, an insertion timing signal generating means 40 generating an insertion timing signal (5) inserting the monitor signal (3) to an idle time slot by a prescribed bit and a detection timing signal generating means 50 taking the timing to detect the position of the monitor signal (3) and generating a detection timing signal (6), are provided. Thus, bit error or missing is detected simultaneously in addition to the line interruption in the time switching circuit 200.
JP62168261A 1987-07-06 1987-07-06 Monitor system for time switching circuit Pending JPS6412640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62168261A JPS6412640A (en) 1987-07-06 1987-07-06 Monitor system for time switching circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62168261A JPS6412640A (en) 1987-07-06 1987-07-06 Monitor system for time switching circuit

Publications (1)

Publication Number Publication Date
JPS6412640A true JPS6412640A (en) 1989-01-17

Family

ID=15864729

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62168261A Pending JPS6412640A (en) 1987-07-06 1987-07-06 Monitor system for time switching circuit

Country Status (1)

Country Link
JP (1) JPS6412640A (en)

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