JPS641334A - Error corrector - Google Patents

Abstract

PURPOSE: To improve the data processing capacity of an error corrector, by providing a syndrome calculating circuit and latch circuit and supplying the output of the syndrome calculating circuit to a correction calculating circuit after the output is once latched by the latch circuit.

CONSTITUTION: A data sequence 1a inputted from an input terminal 10 is stored in a buffer memory 11 and, at the same time, inputted to a syndrome calculating circuit 12 where prescribed syndrome calculation is carried out on the data sequence 1a. The calculated result output 1b of the circuit 12 is latched at the timing of the starting time of a correction calculating circuit 14 and fetched into a latch memory 13. At the correction calculating circuit 14, the latch output 1c of the latch memory 13 is inputted and error correcting calculation is carried out in accordance with a prescribed error correction decoding algorithm during a calculation executing period 1d and, as a result, an erroneous position and the scale of an error are outputted. At a correction processing circuit 15 after the operation of the correction calculating circuit 14 is completed, the data sequence 1a is read out from the buffer memory 11 and the scale of the error is added to the erroneous position. After the error correction, an output 1e is outputted. Therefore, the data processing capacity is improved.

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