JPS6415675A - Circuit for testing integrated circuit - Google Patents

Circuit for testing integrated circuit

Info

Publication number
JPS6415675A
JPS6415675A JP62171078A JP17107887A JPS6415675A JP S6415675 A JPS6415675 A JP S6415675A JP 62171078 A JP62171078 A JP 62171078A JP 17107887 A JP17107887 A JP 17107887A JP S6415675 A JPS6415675 A JP S6415675A
Authority
JP
Japan
Prior art keywords
terminal
integrated circuit
circuit
data
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62171078A
Other languages
Japanese (ja)
Inventor
Takashi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62171078A priority Critical patent/JPS6415675A/en
Publication of JPS6415675A publication Critical patent/JPS6415675A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To reduce the number of parts and to simply perform a test, by providing the external input terminal connected to a testing control signal input terminal and the resistor connected to the control signal input terminal at one terminal thereof and earthed at the other terminal thereof. CONSTITUTION:An integrated circuit 6 to be tested is mounted on a unit 8 and a control signal input terminal 4 is connected to the terminal 3 of a connector 10. When the integrated circuit 6 is operated in a usual mode, the terminal 3 of the connector 3 is opened. By this method, a signal of logic 0 is inputted to the terminal 4 by a resistor 9 and the data of a terminal 1 is outputted to a terminal 7. When a test mode is set in order to test the integrated circuit 6, voltage of +5V is applied to the terminal. By this setup a signal of logic 1 is inputted to the terminal 4 and the data of the terminal is outputted to the terminal 7. The data of the terminal 7 is investigated to judge whether the integrated circuit 6 is normal.
JP62171078A 1987-07-10 1987-07-10 Circuit for testing integrated circuit Pending JPS6415675A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62171078A JPS6415675A (en) 1987-07-10 1987-07-10 Circuit for testing integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62171078A JPS6415675A (en) 1987-07-10 1987-07-10 Circuit for testing integrated circuit

Publications (1)

Publication Number Publication Date
JPS6415675A true JPS6415675A (en) 1989-01-19

Family

ID=15916607

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62171078A Pending JPS6415675A (en) 1987-07-10 1987-07-10 Circuit for testing integrated circuit

Country Status (1)

Country Link
JP (1) JPS6415675A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6127788A (en) * 1997-05-15 2000-10-03 Denso Corporation High voltage discharge lamp device
US6747422B2 (en) 1997-05-16 2004-06-08 Denso Corporation High-voltage discharge lamp device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6127788A (en) * 1997-05-15 2000-10-03 Denso Corporation High voltage discharge lamp device
US6333607B1 (en) 1997-05-16 2001-12-25 Denso Corporation High voltage discharge lamp device
US6747422B2 (en) 1997-05-16 2004-06-08 Denso Corporation High-voltage discharge lamp device

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