JPS641808B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parity circuit used when handling digital information, and particularly to a high-speed parity generation circuit with low power consumption.

[Conventional technology]

An example of the configuration of this type of conventional parity circuit is shown in FIG. 1 is a basic circuit that switches connections between two input terminals and two output terminals using complementary control signals; 2a and 2b are input terminals of the basic circuit 1; 3a,
3b is the output terminal of the basic circuit 1, 4a and 4b are the control signal terminals of the basic circuit 1, and _Q1 and _Q4 are the signals input to the control signal terminal 4b at a high level (hereinafter referred to as "H" level). A transistor that turns on when
Q ₂ and Q ₃ are transistors that turn on when the signal input to the control signal terminal 4a becomes “H” level;
D ₁ ~ _{D o} is the bit information to be parity checked, ₁ ~
D _n is the inversion information of bit information D ₁ to D _o , respectively;
PC is the parity test result, is the parity test result
PC inversion information, V _DD is the power supply voltage. Next, the circuit operation will be described. Bit information D ₁ =D ₂ =…=
Considering the initial state of D _o = “L” (low level), two conduction paths are established in the n basic circuits 1 connected in cascade, and the input terminal and the output terminal 2a of each basic circuit, 3a is “0” V, 2b and 3b
is set to “V _DD ”V. At this time, bit information
The voltage level of D _i = “L” is “0” V, inversion information _i
= “H” voltage level is “V _DD +V _TH ”V.
However, V _TH is the threshold voltage of the MOS transistor. Next, the bit information is parity checked.
When D ₁ to _{D o} are newly determined, input terminals and output terminals 2a and 3a, 2b and 3b in the basic circuit are connected, or 2a and 3b, 2b and 3a are connected, according to those bit information. By this,
Two new conduction paths are formed. At this time, if an odd number of bit information D ₁ to D _o are at "H" level, the output terminal 3a of the final stage is "V _DD ".
V, 3b becomes "0" V. Also, bit information
If an even number of D ₁ to D _o are at "H" level, the output terminal 3a of the final stage becomes "0" V, and the output terminal 3b becomes "V _DD "V. As described above, the parity check of the bit information D ₁ -D _o can be performed by the outputs of the final stage output terminals 3a and 3b.

[Problem that the invention seeks to solve]

According to the conventional parity circuit configuration, the potential of the conduction path changes from “V _DD ”V to “0” V in the worst case.
or from "0" V to "V _DD "V, the time required for the parity check becomes longer. Further, after the conduction path is formed, in a certain basic circuit, charge is extracted through the MOS transistor between the input terminal set to "V _DD "V and the output terminals 2b and 3b. Since this MOS transistor operates near the boundary between the triode region and the saturation region, its on-resistance is large, which significantly reduces charge extraction speed and increases the time required for parity testing.

Furthermore, since a conductive path is always formed, there is a problem in that power consumption is large.

[Means for solving problems]

In order to eliminate these drawbacks, the present invention cascades a plurality of basic circuits each having two input terminals and two output terminals and switching the connections between the input terminals and the output terminals using complementary control signals. A parity circuit that generates parity for a plurality of complementary control signals includes a precharge section that precharges the input terminals and output terminals of all the basic circuits, and a precharge section that precharges the input terminals and output terminals of all the basic circuits, and a plurality of The configuration includes a reference voltage supply section which inputs two types of reference voltages, "H" level and "L" level, through a switch to check the parity of complementary control signals.

[Effect]

With the above-described configuration, the present invention precharges the input and output terminals of all basic circuits when two conductive paths are formed in cascaded basic circuits in the initial state of bit information. After setting the potential and determining the bit information, the parity of the complementary control signal is checked by inputting two types of reference voltages, "H" level and "L" level, via a switch, which connects to the input terminal of the first stage. The potential change of the conduction path is a small amplitude change with respect to the precharge potential, and the input and output terminals of the basic circuit are connected to speed up the time required to determine the parity output of the final stage of the basic circuit.

〔Example〕

FIG. 1 shows an embodiment of the present invention. The same reference numerals as in FIG. 4 indicate the same parts. Here, Q ₅ and Q ₆ are turned on by the clock φ ₁ , and the first stage input terminals 2a,
The transistor _Q7 that sets 2b to the precharge voltage "V _P "V is turned on by the clock _φ2 ,
A transistor _Q8 sets the input terminal 2a of the first stage to "0" V, and is a transistor that sets the input terminal 2b of the first stage to "V _DD "V by the clock φ ₂ .

The circuit operation will be explained. Bit information D ₁ =
Consider the initial state where D ₂ =...=D _o = "L". In this case, two conductive paths are formed in the cascaded basic circuit. Therefore, clock _φ1 is “H”
By reaching the level, the conduction paths, that is, the input/output terminals of all basic circuits are set to "V _P "V.
After this setting is completed, the clock _φ1 goes to the "L" level. Bit information D ₁ to be parity checked next
After ~D _o is determined, the clock _φ2 goes to “H” level, and the input terminals 2a and 2b of the first stage each go to “0”.
V, “V _DD ” connect to V. First stage input terminal 2a
The conduction path leading to is from “V _P ”V to “0”V,
The conduction path connected to the first stage input terminal 2b is “V _P ”
V to “V _DD ”V. In this way, the potential change of the conduction path can be made smaller in amplitude compared to the conventional configuration, and the on-resistance of the MOS transistor forming the conduction path can be reduced, so the output terminals 3a and 3b of the final stage are “0”V,
“V _DD ” V or “V _DD ” V, “0” V is determined at high speed. For example, V _DD = “5”V, V _TH = “1”
Assuming that V, V _P = “2.5” V and MOS transistors of the same size are used, the time required to determine the parity output in this embodiment is approximately the same as in the conventional configuration.
This can be achieved by 0.4 times. In this embodiment, the initial state is set such that the bit information D ₁ =D ₂ =...=D _o = "L", but the bit information D ₁ to _{D o} is undetermined and the control signal of each basic circuit is If terminals 4a and 4b can all be set to the initial state of “V _DD +V _TH ”V,
Transistor _Q5 in the diagram can be removed.

FIG. 2 shows another embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same parts. This is a case where the bit information D ₁ -D _o and the inverted information ₁ - _o all become "H" level before the bit information D ₁ -D _o to be inspected is determined, and is different from "V _P " in the previous embodiment. No external means for generating V is required. _Q9 is a transistor that is turned on by clock _φ3 and precharges the D _i and _i lines of each bit information and inverted information to the "H" level, and _φ3 is a precharge clock for this purpose. FIG. 3 shows the operating clock timing for the embodiment of FIG. Next, the circuit operation will be described. If the bit information D ₁ to D _o is fixed,
The clock _φ3 is at the "L" level, and the two conductive paths are determined to be at the "H" level and the "L" level. Next, the clock _φ2 is set to the "L" level, and each conduction path is brought into a high impedance state, and then the clock _φ3 is set to the "H" level, and the bit information and inverted information _D1 to _D0 , ₁ to _O are all set to " Set to "H" level. As a result, all the transistors in each basic circuit are turned on, and the charge on the previously formed conduction path is distributed, and all of the input terminals and output terminals 2a, 2b, 3a, and 3b of each basic circuit are "H". It is set to an intermediate level (V _P ') between the "L" level and the "L" level. After the bit information _D1 to _D0 to be inspected is determined, the clock _φ2 is set to “H”.
level, and the conduction path formed by the bit information D ₁ to _{D o} is from “V _P ′”V to “0”V, “V _P ′”V
to “V _DD ”V, and the parity check can be performed at high speed as in the previous embodiment.

〔Effect of the invention〕

As described above, the present invention has the advantage that a high-speed parity circuit can be realized by setting the conduction path in the basic circuit for generating parity to an intermediate voltage and performing small amplitude dynamic operation.

In addition, in the conventional configuration, if the bit information D ₁ to _{D o} to be parity checked is undefined and both control terminals are set to "H" level, all MOS transistors in the basic circuit are turned on. ,
This has the disadvantage that power consumption increases due to the creation of a path from the power supply voltage to ground. In the present invention, by using a clock, there is no path from the power supply voltage to the ground, so there is an advantage in reducing power consumption.

Therefore, it is possible to realize a high-speed, low power consumption parity circuit particularly for generating parity in a circuit whose input signal operates dynamically.

[Brief explanation of drawings]

FIG. 1 shows one embodiment of the present invention, FIG. 2 shows another embodiment of the present invention, FIG. 3 shows the relationship between clock timings of the embodiment of FIG. 2, and FIG. 4 shows a conventional configuration. It is a parity circuit. 1...A basic circuit that switches connections between two input terminals and two output terminals by complementary control signals,
2a, 2b...Basic circuit input terminals, 3a, 3b
... Basic circuit output terminals, 4a, 4b ... Basic circuit control signal terminals, Q ₁ , Q ₄ ... Control signal terminals 4
A transistor that turns on when b goes to “H” level,
Q ₂ , Q ₃ ...Transistors that turn on when the control signal terminal 4a goes to "H" level, D ₁ -D _o ...Bit information to be parity checked, ₁ - _o ...Bit information D ₁ -D _o Inversion information, V _DD ... power supply voltage, Q ₅ ~
Q ₉ ...Transistor turned on by a clock,
_φ1 to _φ3 ...Clock, PC...Parity test result,
PC: Reversal information of parity test result PC.

Claims (1)

[Claims] 1 A plurality of basic circuits each having two input terminals and two output terminals and in which the connections between the input terminals and the output terminals are switched by complementary control signals are connected in cascade, and the parity of the plurality of complementary control signals is In the parity circuit that generates a parity circuit, a precharge section that precharges the input terminals and output terminals of all the cascaded basic circuits, and two input terminals of the cascaded first-stage basic circuit, the plurality of complementary A parity circuit comprising a reference voltage supply section which inputs two types of reference voltages, "H" level and "L" level, through a switch to check the parity of a control signal.