JPS6418329U - - Google Patents
Info
- Publication number
- JPS6418329U JPS6418329U JP11277487U JP11277487U JPS6418329U JP S6418329 U JPS6418329 U JP S6418329U JP 11277487 U JP11277487 U JP 11277487U JP 11277487 U JP11277487 U JP 11277487U JP S6418329 U JPS6418329 U JP S6418329U
- Authority
- JP
- Japan
- Prior art keywords
- timer
- built
- value
- commercial power
- microcomputer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Microcomputers (AREA)
Description
第１図は本考案で使用するマイクロコンピユー
タのブロツク図、第２図及び第３図は本考案の発
振回路を示す回路図、第４図は第１図のプログラ
ムのフローチヤート、第５図は従来のマイクロコ
ンピユータの発振回路を示す回路図である。
図中、１は発振入力端子、２はクロツク発振回
路、３および４は分周回路、５は内蔵タイマ１、
６は内蔵タイマ２、７はプログラム格納ＲＯＭ、
８はＲＡＭ、９は入出力バツフア、１０は論理演
算部、１１はアキユムレータ、１２は商用周波数
入力端子である。
Figure 1 is a block diagram of the microcomputer used in the present invention, Figures 2 and 3 are circuit diagrams showing the oscillation circuit of the present invention, Figure 4 is a flowchart of the program in Figure 1, and Figure 5 is a FIG. 1 is a circuit diagram showing an oscillation circuit of a conventional microcomputer. In the figure, 1 is an oscillation input terminal, 2 is a clock oscillation circuit, 3 and 4 are frequency dividing circuits, 5 is a built-in timer 1,
6 is built-in timer 2, 7 is program storage ROM,
8 is a RAM, 9 is an input/output buffer, 10 is a logic operation section, 11 is an accumulator, and 12 is a commercial frequency input terminal.
Claims (1)
おいて、商用電源周波数を基準としてその１サイ
クルをマイクロコンピユータの発振パルスにより
カウントする手段と、このカウント値を分周した
ものを商用電源周波数２サイクル毎に記憶する内
蔵タイマと、この内蔵タイマの値を基準値として
プログラムを進行させる手段とを具備したマイク
ロコンピユータのタイマー装置。 In a microcomputer that uses a built-in timer, there is a means for counting one cycle using the oscillation pulse of the microcomputer based on the commercial power frequency as a reference, and a built-in timer that stores the divided frequency of this count value every two cycles of the commercial power frequency. and means for advancing a program using the value of the built-in timer as a reference value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11277487U JPS6418329U (en) | 1987-07-22 | 1987-07-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11277487U JPS6418329U (en) | 1987-07-22 | 1987-07-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6418329U true JPS6418329U (en) | 1989-01-30 |
Family
ID=31352018
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11277487U Pending JPS6418329U (en) | 1987-07-22 | 1987-07-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6418329U (en) |
-
1987
- 1987-07-22 JP JP11277487U patent/JPS6418329U/ja active Pending