JPS641875B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory output control method used when output data is output from a plurality of memory boards to a bus line.

Conventionally, configurations in which each output data is output from multiple memory boards to a bus line have been widely used, but the memory device and the output circuit, which is the part that outputs data, are usually configured on separate boards. The output circuit is of a type commonly used for each memory board.

That is, as shown in FIG. 1, the outputs of the memory circuits 10 _a , 10 _b , . . . are OR-combined and then output onto the data bus via the output circuit 20 .

One of the memory devices is selected by a memory address given from the outside (more than one memory device does not operate at the same time). Now memory circuit 10
To explain the operation of _a , based on the control of the timing circuit TM _a , data from the memory (usually dynamic RAM) DRAM _a is clocked at the timing when the data is output.
CLK is input to register REG _a .

In the cycle in which new data enters register REG _a , the output is enabled (the signal becomes LOW), and the data in register REG _a can now be transferred to register REG _c of the output circuit 20 via output buffer B _a . ing.

The data in this register REG _c is output to the data bus DB via the output buffer B _c under the control of an output control signal CNT ₁ applied from the outside.

However, in such conventional memory control methods, although the output circuit has a small number of electrical circuit components, the number of signal lines increases when outputting to multiple bus lines, for example. It is difficult to coexist with circuits having the following functions, and since it is configured as a single board like a memory device, it has the drawback of reducing packaging density and being uneconomical.

An object of the present invention is to eliminate such drawbacks, and to provide a memory output that can reduce the number of boards and at the same time reduce signal transfer between boards by incorporating an output circuit into the board of a memory device. The objective is to provide a control method.

The present invention will be explained in detail below using the drawings. FIG. 2 is a block diagram showing a main part of an embodiment of the present invention. Here, a memory circuit in a high-speed arithmetic device operating in synchronization with a machine cycle is shown as an example.

In the figure, memory circuits 30 _a , 30 _b . . . have the same circuit configuration, so the configuration of the memory circuit 30 _a will be explained as a representative. The memory circuit can read new data in the third cycle after the activation of READ (data read signal), and can read the currently stored data arbitrarily until the next data can be read. It is configured so that it can be done.

In the memory circuit _30a , _31a is an output control circuit, and _32a is an output control circuit 31a _.
This is a gate that performs a negative AND operation between the output of CNT1 and the output control signal _CNT1 (output enable). An output enable signal is given to the output control circuit from a central processing unit (not shown), and the data bus
Whether or not data is output to the DB is now controlled. This output enable signal is commonly given to each output control circuit, but
Each memory device has a different address, so
A situation in which they start up and output data at the same time does not occur.

FIG. 3 is a diagram showing details of the configuration of the output control circuit _31a . When reading data from memory DRAM _a to register REG _a , the data ready signal (
READY) is sent out and input to a D-type flip-flop (hereinafter referred to as D-FF) 311.
The D-FF 311 is supplied with a clock 1 as shown in FIG. 4A, and the output Q(B) changes as shown in FIG. 4B. The gate 312 generates the clock signal CLK shown in FIG. 4C from this output Q and the clock 1, and applies it to the register REG _a . This causes the register to read data from memory DRAM _a . on the other hand,
A gate 313 generates a signal from the clock 1 and the Q output of the D-FF 311. This is commonly connected to all memory circuits, and when this signal is output, all memory circuits return their output control circuits to the disabled state.
Only the circuit that issued the BUSREQ signal is then set to the enabled state again. The circuit part for setting this state is a flip-flop 314.
and its peripheral circuits. D-FF314
is for obtaining a control signal (N in FIG. 4) necessary for sending the data in the register to the data bus DB. For the D input of D-FF314,
A signal of the AND of BUSREQ (D in FIG. 4) and the Q output of the D-FF 314 itself is input. Further, a clock 2 having a duty ratio (the period is the same as clock 1) as shown in FIG. 4 is inputted as a clock, and the Q output of the D-FF 314 changes as shown in FIG. On the other hand, D-FF311
A clear signal as shown in FIG. 4 obtained from the logical product of the output of the D-FF 314 and the Q output of the D-FF 314 is applied to the clear terminal.

Flip-flop 314 connected in this way
and its peripheral circuitry operate as follows. If clock 2 becomes active while this output control circuit is making the signal active, the D input of D-FF314 is at high level at this time, so its Q output goes to high level. D- at gate 315
The clear signal becomes active by being ANDed with the high level output of FF311, and D-
FF314 is cleared immediately and its Q output becomes low level. In other words, in the output control circuit with the signal active,
D-FF314 becomes high level once, but immediately becomes low level. On the other hand, if clock 2 becomes active while an active BUSREQ signal is coming from another output control circuit, the Q output of D-FF314 becomes high level because the D input is also high level. ,
Since the output of D-FF311 is low level, the clear signal does not become active, and the D-FF311 output does not become active.
The Q output of FF314 remains at high level.
Thereby, even if the Q output of the D-FF 314 was at a low level as a result of the operation in the previous cycle, it is changed to a high level.

The gate _32a performs the negative AND of the Q output of the D-FF 314 and the output enable commonly given to all memory circuits (H in Figure 4), and outputs it to the register.
It is now possible to obtain an enable signal (N in FIG. 4) that enables data transmission from REG _a .

Since the Q output of D-FF314 changes as described above depending on whether the signal is spontaneous or external,
The enable signal can be obtained only when the signal is generated spontaneously, and when the signal is generated elsewhere, it is possible to reliably prevent the enable signal from being obtained by mistake.

In this way, only data from the designated memory circuit is output onto the data bus. In addition,
In cycles where BUSREQ is not output from any memory circuit, the output control circuit remains in the same state as the previous cycle.

As described above, according to the present invention, it is possible to output data to a data bus without requiring a board dedicated to an output circuit and with reducing the number of signal transfers between each board. can.

Further, according to the present invention, it is possible to contribute to a reduction in the number and types of boards, and furthermore, since each circuit is equipped with a circuit that determines which board outputs the output, it is possible to insert the board into any slot. There are advantages.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional memory device, FIG. 2 is a configuration diagram of an embodiment of the memory device according to the present invention,
Figure 3 is an example diagram of the output control circuit, Figure 4
The figure is a time chart for explaining the operation of each part. DB...data bus, _30a , _30b ,...memory circuit, _31a ...output control circuit, _32a
...Gate, DRAM _a ...Memory, REG _a ...Register, 311, 314...D-FF, 312,
313, 315, 317...gate, 316...
Batsuhua.

Claims (1)

[Scope of Claims] 1. An output control method for a plurality of memories each connected to a common data bus through an output buffer and operating over several machine cycles in synchronization with a machine cycle, which A plurality of gates each transmitting an output enable signal given through one common signal line to a plurality of output buffers; a plurality of control means for controlling opening and closing, each control means: means for outputting an active level signal to the second common signal line when opening the corresponding gate; and a means for outputting an active level signal to the second common signal line when opening the corresponding gate. An output of a memory characterized by having means for temporarily closing the gate in accordance with a signal of the second common signal line, and means for further opening the gate when the second common signal line is set to an active level. control method.