JPS641977B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention is a digital to analog converter (hereinafter referred to as
(abbreviated as DAC), and in particular relates to DAC circuit means suitable for use in MOS monolithic ICs. Figure 1 shows Mr. Adib Al Hamadeh.
It was invented by R.
A conventional example of a DAC circuit means suitable for a MOS monolithic integrated circuit disclosed in Japanese Patent No. 28851 will be shown. The details of this circuit means were reported in detail by Mr. Hamade at the International Solid State Circuit Conference held in Philadelphia, USA in 1976, so only a brief explanation will be given here. Figure 1 shows 3-bit digital input
In the example of a DAC, A, is the most significant bit (MSB) digital complementary input, B, is the second bit digital complementary input, and C, is the least significant bit (LSB) digital complementary input. ²³ -1 tap potentials are obtained by ²³ resistors connected in series between the reference voltage terminal and the ground voltage terminal, and the tap potential corresponding to the digital input is converted into analog by a decoding circuit composed of MOSFET switches. Guided to the output terminal OUT.
The converter with this configuration has a simple configuration, MOS
Its features include a circuit configuration suitable for monolithic integrated circuits and essentially monolithic input/output characteristics. However, although the conversion circuit having this configuration is of a voltage output type, it has a drawback in that its output impedance is high. Therefore, the conversion circuit having this configuration is a circuit means suitable for application to an analog-to-digital converter in which a DAC output is applied to a comparator having a high input impedance, and a comparison operation is performed with an unknown analog input to the comparator. This application example is also disclosed in the above-mentioned publication. On the other hand, when used as a DAC, the allowable load range is extremely narrow, and a buffer amplifier is definitely required for the output. Further N bits
In the DAC, N MOS switches are connected in series between the tap of the resistor network and the analog output terminal, and this conversion circuit means has the disadvantage that the switching speed decreases and high-speed conversion cannot be performed. An object of the present invention is to provide a high-speed DAC that is suitable for simple layout means. The DAC according to the present invention has unit current source switch cells composed of a current source and a current switch arranged in a matrix, so it can have a simple layout, has extremely high output compliance characteristics, and can operate with a single current. that it is possible,
It is a circuit means suitable for MOS monolithic integrated circuits, has essentially monotonic characteristics, and is a current output type, so high speeds are possible. The configuration, operating principle, and embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 2 shows the basic configuration of the DAC of the present invention, and shows an example of a 6-bit digital input converter. 11 is the most significant bit (MSB) digital input terminal, and 12, 13, 14, 15
are second, third, fourth, and fifth bit digital input terminals, respectively, and 16 is a least significant bit (LSB) digital input terminal. 2, 3, 4
is an encoding circuit and consists of ROM (read only memory). Reference numeral 10 denotes current source switch cells arranged in rows and columns, and each current source switch cell has the same shape and is arranged adjacently in a matrix. The first encode circuit 2 described above creates eight first encode signal groups A0 to A7 from the upper three bit signals of the digital input, and sends them to signal lines 20 to 20, respectively.
27, the corresponding signals A0 to A7 are supplied to the current source switch cells belonging to the same column. Here, the 0th to 7th columns are indicated by numbers 100 to 107, respectively. Therefore, for example, the signal line 20 is
A signal A ₀ is commonly supplied to all current source switch cells belonging to the column 100. The second encoding circuit 3 further encodes the signals of the first encoded signal group A0 to A7 to create a second encoded signal group B0 to B7, and connects the signals to current sources belonging to the same column through signal lines 30 to 37, respectively. Signal B0 corresponding to switch cell
~B7 is supplied. On the other hand, the third encoder circuit 4 converts the fourth and fifth bits and the least significant bit digital input signal into C.
Eight third encode signal groups 0 to C7 are created and the corresponding signals C0 to C7 are supplied to current source switch cells belonging to the same row through signal lines 40 to 47, respectively. Here, the 0th to 7th lines are indicated by numbers 110 to 117, respectively. Therefore, for example, the signal line 43 commonly supplies the signal C3 to all current source switch cells belonging to the third row 113. The output current from each current source switch cell is 50~
It can be taken out from the terminal 5 through the output line indicated by 57. Although FIG. 2 shows an example of a single analog output configuration, it goes without saying that a complementary current output type configuration is also possible. As is clear from the above explanation, the DAC of the present invention has the first, second, and third DACs.
Its basic components include an encoding circuit, first, second, and third encoding signal groups from each encoding circuit, a group of current source switch cells arranged adjacently in a matrix, and current output means. Next, the operating principle of the DAC of the present invention will be explained. The configuration example shown in Figure 2 is a 6-bit DAC, and the input/output range of the DAC is set to 8 by the upper 3 bits.
It can be divided equally into segments. Now define the 0th segment for the code 000 of the upper three bits of the digital input code, and the 1st to 7th segments from the code 001 to the code 111 in order. The 0th segment is 000000 to 000111
Up to 8 sets of codes belong to the first segment.
Eight sets of codes from 001000 to 001111 belong, and similarly, eight sets of corresponding digital input codes belong to each segment up to the seventh segment. In the configuration example shown in FIG. 2, ²⁶ = 64 current source switch cells corresponding to 6 bits are arranged in a matrix with 8 rows x 8 columns as a current source switch cell group 10, and each column has 100 to 100 current source switch cells. The current source switch cells belonging to 107 correspond to the 0th to 7th segments, and the current source switch cells belonging to each row 110 to 117 correspond to the addition weight bits determined by the lower three bits. For example, now the digital input is
When the code is 011101, the upper 3 bits are 011
All the current source switch cells up to the third segment are set to the output state in response to the code 101, and the five current source switch cells corresponding to the code of the lower bit of 101 in the fourth segment are set to the output state,
By disabling the other three current source switch cells in the fourth segment and all current source switch cells belonging to the fifth, sixth, and seventh segments, an analog output current corresponding to the code 011101 is obtained. things become possible. Tables 1 and 2 show suitable input/output code characteristics of the encoder circuit that enables such an operation.

【table】

【table】

[Table] The second encoder outputs a group of encoded signals B0 to B7 that select segments to be prohibited. As shown in Table 1, for example, for the upper 3 bit code 011, the codes B0 to B7 are
00001111, the signals from B4 to B7 become 1, and the fourth to seventh segments are prohibited, and the signals from B0 to B7 become 1.
The signals up to 3 become 0, and the 0th to 3rd segments are no longer in the prohibited state. The encode signal group A0 to A7 output from the first encoder supplies a signal of "1" to the highest segment among the segments that are not in the inhibited state, and the on/off of the current source switch cell belonging to this segment corresponds to the lower 3-bit digital input signal. A signal of “0” is supplied to the remaining segments, and all current source switch cells belonging to the remaining segments are always on (output) without depending on the lower 3-bit digital input signal. Control as much as possible. As shown in Table 2, for example
For the upper 3 bit code of 011, A0 to A7
The code becomes 00010000 and the third segment is selected. The output signal of the third encoding circuit turns on (outputs) a predetermined number of current source switch cells belonging to the segment selected by the second encoding circuit, depending on the lower 3-bit digital input signal, and turns on (outputs) the remaining cells. It outputs a group of encoded signals C0 to C7 that turn the cells off (inhibited). As shown in Table 3 ab, for example, for the lower bit code of 101, the code of C0 to C7 becomes 00000111, the signal of C5 to C7 becomes 1, and the signal of C0 to C4 becomes 1.
becomes 0. Therefore, among the current source switch cells belonging to the segment (column) selected by the upper bit, the current source switch cells belonging to the 5th to 7th rows are disabled (off), and the current source switch cells belonging to the 0th to 4th rows are disabled. Becomes output (on) state. According to the operating principle explained above, the DAC of the present invention
operates, and depending on the increase in the digital input code, the output currents of the respective current source switch cells are added to obtain the output current, resulting in an essentially monotonic characteristic. Next, specific embodiments of the basic components of the DAC of the present invention will be described with reference to the drawings. Figure 3 shows the basic circuit configuration 2 of a current source switch cell.
00 is shown. 280 is the power wiring and terminal 28
1 and 282 to automatically connect to adjacently located current source switch cells. Similarly, 270 is a ground wiring connected via terminals 271 and 272, 260 is a wiring that supplies the gate bias voltage of the current source FET 290, and the terminal 26
1,262 is connected to the gate of FET290, and 250 is an analog output wiring and terminal 25
Switch FET29 connected through 1,252
1 drain is connected. Further, 220 is an output signal line of the first encoder circuit 2, which is connected via terminals 221 and 222, and 230 is an output signal line of the first encoder circuit 2, which is connected via terminals 221 and 222.
The output signal line of the encoder circuit 3 is connected to the terminal 231,
232, and 240 is an output signal line of the third encoder circuit 4, which is connected via terminals 241 and 242. As described above, each wiring is automatically connected to other current source switch cells arranged adjacently. As mentioned above, 290 is a current source FET, and the FETs of each current source switch cell are commonly biased. By making the current source FETs of all cells the same shape, each current switch cell turns on and off a unit current, and a DAC whose input and output characteristics are in a linear relationship is constructed. On the other hand, the shape of the current source FET in each segment is the same, and by applying binary weighting to the current source FET belonging to the 0th to 7th segments,
A DAC with nonlinear characteristics for PCM is constructed. The drain of current source FET290 is a switch FET
291 source. switch
The gate of FET 291 is biased by the output of a multi-input logic gate, ie, an AND-NOR circuit shown at 292 and 293. This multi-input logic gate can have various combinations depending on whether the positive or negative logic level FET of the control signal is a P channel or an N channel, but an ANDNOR circuit configuration is shown here as an example. The first input terminal of the two-input AND circuit 293 is connected to the output signal line 220 of the first encoding circuit, and the second input terminal is connected to the output signal line 220 of the third encoding circuit.
42, the output of the 2-input AND gate 293 is connected to the first input terminal of the 3-input NOR gate 292, and the second input terminal of the 3-input NOR gate 292 is connected to the output signal line 23 of the second encode circuit.
0, the third input terminal is connected to the current source
Connected to the common tangent point between the drain of the FET and the source of the switch FET. Next, the operation of this current source switch cell will be explained. When the level of the output signal of the second encode circuit 3 applied to the second input terminal of the NOR 292 via the wiring 230 is at a high level, the NOR gate 2
The output of 92 becomes low level, and switch FET2
91 is cut off. Therefore, the output signal of the second encoding circuit operates as an inhibition signal. On the other hand, when the level of the output signal of the second encoding circuit is at a low level, the inhibited state of the cell is released, and the output state of the cell is controlled by the output signals of the second and third encoding circuits. When the level of the output signal of the first encoding circuit applied to the first input terminal of AND gate 293 is at a low level, the output signal of the third encoding circuit is applied to the second input terminal of AND gate 293. Regardless of the level of
The first and second input terminals of the NOR gate 292 are at a low level, so the NOR gate 292 operates as an inverting amplifier with the third input terminal connected to the terminal 295 as the input and 296 as the output, and the FET 291 is feedback biased and turned on. Therefore, this cell outputs a current to the output line 250. On the other hand, the level of the output signal of the second encoding circuit is at a low level and the inhibited state of the cell is released, and the level of the output signal of the first encoding circuit applied to the first input terminal of the AND gate 293 is When flips to high level, AND gate 293
The output state of the cell is determined depending on the level of the output signal of the third encoding circuit applied to the second input terminal of the cell. When the level of the second input terminal is high, the output of the AND gate 293 is high, the output of the NOR gate 292 is low, the switch FET 291 is cut off, and the cell is turned off (inhibited). On the other hand, and gate 2
The output of 93 becomes low level, and the Noah gate 292
operates as an inverting amplifier with terminal 295 as input and 296 as output, switch FET 291 is feedback biased and turned on, and this cell is connected to output line 2.
Outputs current to 50. As explained above, the current source switch cell shown in FIG. 3 operates as intended as a basic component of the DAC of the present invention. Furthermore, this current source switch cell significantly improves the output impedance without complicating the configuration of a conventional analog current switch, and as a monolithic integrated circuit, it can be used as a DAC with extremely good output compliance characteristics.
This is a preferred embodiment for realizing this. The output compliance characteristic of a DAC is a characteristic that suppresses changes in the output current with respect to the voltage amplitude of the analog current output terminal, and is one of the basic characteristics of a current output type DAC. However, it becomes impossible to satisfy the accuracy. In the current source switch cell shown in Fig. 3,
When the first and second input terminals of the NOR gate 292 are at a low level first and the NOR gate 292 is operating as an inverting amplifier, a closed feedback loop is formed from the source to the gate of the switch FET 291. Now assuming that switch FET291 and current source FET are of the same shape, the transconductance of these FETs is gm, and the output impedance is
Let r ₀ , the potential of the drain of the switch FET, that is, the potential of the output terminal, be V ₅ , and the potential of the switch FET291
The potential of the common connection terminal 295 between the source and the drain of the current source FET 290 is V295, and the output current is _I5 ,
The output current I ₅ when the gate bias voltage of the current source FET is V _G can be approximated as follows. I ₅ = (V ₅ −V ₂₉₅ )/γ ₀ + (−μ)・gm・(−V ₂₉₅ )
…(1) Next, consider the output conductance. The change in output current ΔI ₅ due to the potential change ΔV ₅ at the output terminal is ΔI ₅ = (ΔV ₅ −ΔV ₂₉₅ ) /γ ₀ +(−μ)・gm・(−ΔV ₂₉₅ )…(2) At this time, ΔI ₅ = ΔV ₂₉₅ / γ ₀ , so ΔI ₅ = 1/(2−μ・gm・γ ₀ )γ ₀・ΔV ₅ …(3) 1/−μ・(gm・γ ₀ )・γ ₀・ΔV ₅ …(4) Therefore, the output conductance ΔI ₅ /ΔV ₅ is the following formula
It can be approximated as (5) ΔI ₅ /ΔV ₅ = 1/−μ・(gm・γ ₀ )・γ ₀ …(5) Note that (−μ) is the gain of the NOR gate 292 that operates as an inverting amplification amplifier. . The impedance (reciprocal of the output conductance) obtained in the conventional simple differential current switch format is (gmr ₀ )·r ₀ , and the cell shown in FIG. 3 has achieved an improvement of a factor of μ. It is well known in the art that it is easy to increase the gain μ of a NOR gate operating as an inverting amplifier to 10 times or more. In experiments conducted by the present invention, the fluctuation of the output current was 0.00375% for an amplitude of 10 V of the output voltage, and the fluctuation rate was 0.000375%/V. The least bit (LBS) value of a 12-bit DAC is approximately 0.025% of the full-scale value, and if an error equivalent to 1 LSB is allowed, then a DAC using the current source switch cell of the present invention will allow an amplitude of 64V. Ru. On the other hand, when a simple differential analog current switch is used, the characteristics deteriorate by 1/μ. The gain of the inverting amplifier used in the experiment was 16, so if a conventional differential analog current switch was used, the output permissible amplitude would be significantly reduced to 4V. Next, an embodiment of the first and second encoding circuits 2 and 3 will be described with reference to FIG. Each encoding circuit can be achieved with a ROM circuit. In this ROM circuit, the solid lines indicate input/output signal lines, and the small circles at the intersections of the solid lines indicate switch FETs. I get the output. This means of describing a ROM circuit is well known and obvious to those skilled in the art, so a more detailed explanation will be omitted here. In response to the digital input of the upper 3 bits of “101”, the output signal lines 20 to 2 of the first encoder 2
Since at least one of the switch FETs on the output line 24, 26, and 27 is turned on, the outputs A0 to A4 and A6, A7 are both at low level, and the output A5 is that none of the switch FETs on the output line 25 is turned on.
only have a high level. An embodiment of the second encoding circuit 3 whose inputs are the output lines 20 to 27 of the first encoding circuit 2 is also shown in FIG. Similarly to the above, for the digital input of the upper 3 bits of “101”, the signal line 2
Since only the signal A5 of No. 5 becomes high level, the switch FET on the output signal lines 30 to 35 of the second encoder circuit turns on, so the outputs B0 to B5 both become low level, while the signal A5 on the output lines 36 and 37 turns on. Since neither switch FET is turned on, B6,
B7 becomes high level. The embodiments of the first and second encoder circuits outlined above satisfy the input/output code relationship shown in Table 1. FIG. 5 is an embodiment of the third encoding circuit for encoding the lower digital input signal, and is a ROM
It consists of a circuit, ROM4A, and ROM4B. For example, only the output line 62 of the ROM 4A is at a high level for the lower three bits of digital input 010. Therefore, in ROM4B, only the data C0 and C1 on the output lines 40 and 41 are at low level, and the encoder circuit composed of ROM4A and 4B is a preferred embodiment of the third encoder circuit, and is shown in Table 2. The relationship between the input and output codes shown is satisfied. Figure 6 shows the current source switch cell shown in Figure 3.
An example implemented using an integrated circuit with a CMOS structure is shown. Parts common to those in FIG. 3 are given the same numbers. FET301 and 302 are n-channel
The FETs 303 and 304 are p-channel MOSFETs and constitute a NOR gate 292. Furthermore, FETs 314 and 313 are p-channel MOSFETs, FETs 311 and 312 are n-channel MOSFETs, and the AND gate 2
93 and constitutes a composite logic gate together with the gate 292. This current source switch cell with a CMOS structure does not consume power in the control circuit in a steady state, so it can constitute a low power consumption DAC. Figure 7 shows the current source switch cell shown in Figure 3 as an enhancement/depression n-channel.
An example implemented using a MOS (E/D NMOS) integrated circuit is shown. Parts common to those in FIG. 3 are given the same numbers. Here, an example is shown in which a depletion FET is used as the current source FET 290.
In this case, there is an advantage that wiring for the gate bias of the current source FET is not required, but there is a disadvantage that the absolute value of the output current fluctuates greatly depending on variations in the threshold voltage of the FET 290, temperature changes, etc. Therefore, although this circuit means is not suitable for a particularly high-precision DAC, it is effective as a DAC circuit means for special applications such as low-quality audio output. In Figure 7, FET301, 302, 31
1,312 is an enhancement type channel
FET, the channels 301 and 302 constitute the NOR gate 292 part, the FETs 311 and 312 constitute the AND gate 293 part, and the FET 310 is a depletion type n-channel FET,
They are commonly connected to the circuit as a load, reducing the number of elements in the cell. Although the current source switch cell with this E/DNMOS' structure increases power consumption in the control section, it has a small number of elements, and when implemented in an integrated circuit, the cell occupies a smaller area, making it an economically superior circuit means. be. FIG. 8 shows an embodiment of a portion of the current source switch cells 10 arranged in rows and columns in the configuration of the DAC of the present invention shown in FIG. Second
The same numbers are given to the parts common to the figures or FIG. 3. The basic cell structure is shown in Figure 7.
Although this is a DNMOS type current source switch cell, an enhancement n-channel FET to which a bias voltage is supplied from the outside is used as the current source FET to improve accuracy. FIG. 8 shows an example of means for sharing wiring between cells for economical cell layout. As illustrated, the output current extraction wiring 250, the bias voltage supply wiring 260, the ground wiring 27, and the VDD power supply wiring 28 can be laid out in common between cells, and the dedicated chip area can be reduced. Figure 9 shows the current source FET of the embodiment shown in Figure 8.
This is an example of an external biasing means. Reference numeral 403 denotes a reference voltage source circuit configured between the power supply VDD and ground, and it may be configured in the same integrated circuit chip as the DAC, or it may be configured as an external circuit. 400 is an operational amplifier, resistor 405
and a reference current source FET 410 constitute a voltage-current converter. Resistors 407 and 409 are dividing resistors that provide a stable bias potential to terminal 408. FET411, gates 413, 412 are the reference current source FET410, which is the current source in the cell.
This is an additional circuit for placing the FET group 490 in the same bias state, and in the output state of each cell,
Since the current source FET of each cell and this reference current source FET are biased so that the gate-source voltage and drain-source voltage are the same, the temperature at the input threshold level of the NOR gate 292 that operates as an inverting amplifier in the cell A highly stable DAC can be realized by tracking the reference current I _Ref and the output current of the DAC against fluctuations in the power supply. As explained above, the DAC of the present invention is a MOSFET
We provide DAC circuit means suitable for configuring as an integrated circuit, and especially suitable for manufacturing using very high density integrated circuit (VLSI) technology, which is expected to further develop in the future as LSI for memory circuits develops.
Provides circuit means for DAC. By providing circuit means that can obtain even higher output compliance characteristics, it is possible to realize a high-precision DAC using VLSI technology.
Furthermore, as shown in the examples of the CMOS structure or E/DNMOS structure, it enables circuit configurations aimed at lower power consumption and economical chip layout, and is also a current output type, enabling higher speeds.
Furthermore, since the control circuit is comprised of conventional normal logic circuits, it naturally operates from a single 5V power supply, which furthermore enables essentially monotonic characteristics.
Compatibility with normal digital circuits including circuit power supply means has been achieved. As described above, the DAC of the present invention greatly contributes to the development of this technical field.

[Brief explanation of drawings]

Figure 1 shows a conventional DAC, Figure 2 shows the configuration of the DAC of the present invention, and Figure 3 shows the configuration of the DAC of the present invention.
FIG. 4 is a diagram showing the basic configuration of the current source switch cell section of the DAC. FIG. 4 is a diagram showing an embodiment of the first and second encoders of the DAC of the present invention. FIG.
Figure 6 is a diagram showing an embodiment of the third encoder of the present invention.
7 is a diagram showing an embodiment of the current source switch cell portion of the DAC of the present invention using E/D NMOS, and FIG. 8 is a diagram showing an example of the current source switch cell portion of the DAC of the present invention arranged in a matrix. Partial equivalent circuit diagram of the embodiment, FIG. 9 is a diagram showing an embodiment of the external bias means of the DAC of the present invention. 11-16... Digital input, 2, 3, 4... Encoding circuit, 10... Current source switch cell matrix.

Claims (1)

[Claims] 1. A plurality of unit current source switch cells arranged in a matrix, each having a current source, a switch for extracting current from the current source, and a multi-input logic circuit for controlling the switch, and for each row of the unit current source switch cells. first and second signal line groups provided and commonly connected to the multi-input logic circuit in the row;
A third signal line group provided for each column of the unit current source switch cells and commonly connected to the multi-input logic circuit of that column, and a current of the unit current source switch cells whose switches are turned on. an output line that outputs the sum of the signals, and a first control signal that selects one of the first signal lines of the first signal line group that corresponds to the number signified by the signal of a predetermined number of bits from the most significant bit of the input digital signal. and a second control signal applied to a number of signal lines of the second signal line group that is one less than the number indicated by the predetermined number of bits of the input digital signal. a second encoder that generates a second encoder, and a number of signal lines of the third signal line group corresponding to the number of bits other than the predetermined number of bits from the most significant bit of the input digital signal. a third encoder that generates a third control signal, and when the first control signal is applied, the multi-input logic circuit turns on the switch in response to the third control signal; When the second control signal is applied, the third
A digital-to-analog converter, characterized in that the switch is configured to turn on regardless of a control signal.