JPS641987B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention provides a circular transmission path for data transmission.
The present invention relates to a data highway system in which a single highway monitoring device and a plurality of station nodes are connected on the transmission path in a double manner, and data is exchanged between arbitrary station nodes.

In general, a data highway system has one highway monitoring device SV and a plurality of station nodes ST connected in a ring, and each station node has a processing device CPU and an input device IO. The device is configured to connect devices such as the station node and exchange data between arbitrary devices via a station node. As will be described later, the data format flowing through the transmission path consists of a frame header section and a data section, and a synchronization flag for establishing synchronization of the transmission path is added to the frame header section. Each station node establishes synchronization using this synchronization flag and sends and receives data.

Traditionally, this type of data highway system
A synchronization flag is sent from the SV, and each station node exchanges data while establishing synchronization using this synchronization flag.

If the working system goes out of synchronization due to a failure on the transmission path or a station node, the backup system is used, and if the backup system goes out of synchronization, the reliability of the system is increased so that communication can be performed using the working system. It's improving.

In the conventional method, when station nodes are scattered over a large campus, when out-of-synchronization is detected, even if the highway monitoring device can know that the failure has occurred, the failure detection node cannot be known, so all station nodes It was necessary to inspect and inspect the equipment, which required a large amount of time for investigation and restoration.

An object of the present invention is to eliminate the above-mentioned problems and provide a data highway method that can detect faulty nodes at locations such as computer centers where SVs are installed. In a data highway system in which one highway monitoring device and multiple station nodes are connected to a road, and communication is performed between arbitrary station nodes, if a loss of synchronization occurs on the transmission line or station node, a backup system is used. When normal single-system operation is possible, the highway monitoring device uses a specific area within the data format frame flowing on the transmission path to reconfigure the transmission path. The present invention is characterized in that a polling operation is performed on all the connected station nodes, and out-of-synchronization detection information is collected from the station node where the out-of-synchronization has occurred.

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 is a configuration diagram of a data highway system according to an embodiment of the present invention, in which SV is a highway monitoring device, ST is a station node, L is a transmission line,
CPU is a processing unit, and IO is an input/output device.

As is clear from FIG. 1, the data highway system of the present invention has transmission paths L0 and L1 that can be shared for data transmission in opposite directions, and includes a highway monitoring device SV, station node ST ₀ ,
ST ₁ , ST ₂ , . . . ST _o-1 , ST _o are connected to form a circular data highway system.

FIG. 2 shows data format frames flowing on a transmission path. As is clear from the figure, a frame consists of a frame header section and a data section.
The frame header section further includes a synchronization flag SYNC,
Node address NADR, node command
NCMD consists of node response NRES.

Figure 3 shows the above SYNC, NADR, NCMD,
This is a detailed diagram of NRES. The synchronization flag SYNC is a fixed pattern, and in the example system,
It has a code pattern of “01001100”. The node address NADR consists of station node addresses AD ₀ -AD ₅ , a busy indication bit USE, and a parity bit P. The in-use display bit USE indicates unused when it is "0" and in use when it is "1". The node command NCMD is
Operation code OP ₀ ~ OP ₂ , unused bits
NU, individual/common specification display bit GNRL, line switch instruction bit LSW, power cut instruction bit
The details of the operation code sections _OP0 to _OP2 , which consist of PWOF and parity bit P, are shown in FIG. Individual/common designated display bit
GNRL instructs that only the station node designated by NADR operates when it is "0", and that all station nodes operate when it is "1". Line switch instruction bit LSW is “0”
When it is "_0" , it specifies the use of the transmission line L0, and when it is "0", it specifies the use of the transmission line _L1 .

Finally, the node response NRES includes the specified node response bit NRES, the station node synchronization error bit SYCK, the station node power error bit PWCK, the station node memory error bit MECK, and the station node synchronization error bit SYCK.
Logic error bit LGCK, station node/loopback display bit WRAP, unused bit
It consists of NU and parity bit P.

The SV always sends frames in the format shown in Figure 2 onto the transmission path. Each station node uses the synchronization flag SYNC in the frame header.
Establishes synchronization with the transmission path and sends and receives data in the data section. In addition, the station node constantly monitors the node address NADR in the frame header.
It has a function of writing a response to a command NCMD addressed to its own node in the node response section NRES.

For example, if an out-of-synchronization is detected on line L ₀ of ST ₂ in FIG. 1, the transmitted data on line L ₀ of ST ₂ is not guaranteed. Therefore, the out-of-synchronization is also detected on the line _L0 side of the station nodes ST _o-1 and ST _o . Also, the frames sent by SV are
When it goes around line L ₀ and returns, the SV similarly detects an out-of-synchronization. When the SV detects a loss of synchronization, it performs a line switch operation for all nodes on the transmission path using other systems. The line switch operation is to switch the data that has been taken in from line _L0 to line _L1 .
This switching is done using the node command NCMD from SV.
This is done by setting the GNRL bit to "1" and the LSW bit to "1" and sending the command to all nodes. Then, after switching the SV to another system,
When the other system is operating normally, this normal system frame is used to individually poll all station nodes connected to the transmission path. In polling, first specify the node address of ST ₀ in the node address NADR of the frame header section, read the status of ST 0 by writing the node response NRES to ST ₀ , and then read the status of ST ₀ sequentially until the last ST _o . Perform the action. Since each station node ST stores the fact that synchronization has occurred using a flip-flop, etc., when polling is applied from the SV, the node response NRES shown in Figure 3 is
Set the SYCK bit inside to "1" to perform an error operation.

In SV, by creating a table based on the responses collected from each station node, it is possible to know which node first detected an out-of-synchronization. For example, the line between ST ₁ and ST ₂ shown in Figure 1
Assuming that a synchronization error occurs due to a failure in L ₀ , when the above polling is performed from the SV, synchronization errors will be reported from all station nodes from ST ₂ to ST _o .
SV can recognize a fault in line L ₀ between ST ₁ and ST ₂ above.

Next, FIG. 5 is a block diagram of an SV according to an embodiment of the present invention. In Figure 5, REP is a repeater that has the function of extracting data components and clock components from serial data flowing on a transmission path, and since the transmission path is duplicated, two units are installed in one SV, and LSW E.MEM is a line switch that has the function of switching the receiving lines L ₀ and L ₁ of a duplex transmission path, and E.MEM is a memory and S/MEM that adjusts the frames flowing on the transmission path to a constant cycle.
PREG is a register for converting serial data on the transmission path to parallel data, REG #0 to 2
is a buffer register, MPX is a multiplexer for sending synchronization flags, node addresses, and node commands depending on the transmission timing, and P/S
REG is a register for converting parallel data back into serial data, SYNC is a group of registers for establishing synchronization with data on the transmission path, R-
TIM is determined by the clock component from the received data.
A circuit that has the function of creating the necessary timing inside the SV, S-TIM is a circuit that has the function of creating the necessary timing sent to the transmission line from the oscillator of this circuit, FHD SYNC is the synchronization pattern generation circuit of the frame header, FHD NADR is a circuit that has the function of managing node addresses connected on the highway, FED NCHD is a circuit that controls commands issued to station nodes on the highway, and TABL is a table of data responded by node responses. This is a circuit that creates

Next, FIG. 6 is a block diagram of a station node according to an embodiment of the present invention. In Figure 6
REP is based on serial data flowing on the transmission path.
It is a repeater that has the function of extracting data components and clock components, and since the transmission path is duplicated, two units can be installed in one station node.
LSW is the receiving line L ₀ of the duplex transmission line,
A line switch with the function of switching L ₁ ,
S/P REG is a register for converting serial data on the transmission path into parallel data.
#0 to 2 are buffer registers, MPX is a multiplexer that switches between sending data and sending command responses depending on the timing, and P/S
REG is a register for converting parallel data back into serial data, ADR/COMP is a circuit that has a setting comparison function for station node address and channel address, SYNC is a group of registers for establishing synchronization with data on the transmission path,
COMMON CONT is a common control unit of the station node that controls data transmission and reception of the channel unit and node response, etc.
CONT controls data transmission and reception between the CPU and I/O, and R BUFFER is a buffer memory for received data.
Something that sends data to the I/O side, S
BUFFER is buffer memory for sending data,
What is once converted into packets and sent out to the transmission path,
Since the station node does not have an oscillator, the TIM consists of a circuit that creates the necessary timing signals from the received clock components, and the ERR REG consists of a flip-flop FF for collecting various error information, and provides common control and timing section instructions. It has the function of responding to the node response section.

Next, the operation of the circuit shown in FIG. 5 will be explained.

The S-TIM is a circuit that has a clock source to send frames to a transmission path and creates timing for sending frames. MPX is switched by the timing signal from S-TIM, and the second
Send the frame shown in the figure. The data sent from MPX is 8-bit parallel data, and this data is converted into serial data. Conversion is performed at P/S REG and sent to the transmission line via repeater REP.

The data that goes around the transmission path and returns is sent to the repeater REP.
The data component and clock component are extracted from the bit serial data. The clock component enters the R-TIM circuit to create clock and timing signals necessary for reception operation inside the SV.
The data component enters the line switching circuit LSW and SV
The data from the line specified in E
Enter MEM. E MEM is a memory for adjusting frames flowing through a transmission path to a constant cycle.
The data read from E MEM enters the synchronization flag detection circuit SYNC, which detects the synchronization flag in the frame header. The timing signal from R-TIM becomes valid when synchronization is established.

The data enters a register S/P REG for converting serial data into parallel data and is converted into parallel data. Parallel data passes through buffer registers, REG#0~2,
It is sent to the transmission path via MPXP/S REG and REP.

The explanation will continue assuming that synchronization is detected on the ST ₂ L ₀ side in FIG. 1. When detected on the L ₀ side of ST ₂ , the station nodes and SVs connected after the L ₀ side of ST ₂ also become out of synchronization. In other words,
Out-of-synchronization is detected on the _L0 side of ST _o-1 , ST _o , and SV. When the SYNC circuit in the SV detects synchronization, the node command in the frame header is
Set the LSW bit to 1 and send the frame.
Frame transmission is as described above. Each station node switches the transmission path from L ₀ to L ₁ using an LSW command.

The SV switches from the active system to the backup system and reconfigures the transmission path. Next, the station nodes connected within the transmission path are checked to see if any out-of-synchronization has been detected. This check writes the address of ST ₀ to the address field in the frame header and sends the frame. On the other hand, ST ₀ has not detected the synchronization loss, so the SYCK in the response part of the frame header part is
It responds with “0” and notifies the SV. Similarly, ST ₁ is also polled. The response to this polling is also "0". Next, similar polling is performed on ST ₂ , but since ST ₂ has detected an out-of-synchronization, the response is "1". Similarly, polling is performed for ST _o-1 and ST _o . Under the control of the microprocessor built into the TABL circuit, the SV first determines the address of the station node where the synchronization has been detected.

Next, the operation of the circuit shown in FIG. 6 will be explained.

Frames from the transmission path enter the repeater REP, where they are converted from bit serial data to data components,
Clock components are extracted. The clock component enters the timing generation circuit TIM. Since the station node does not have an oscillator, the clock and timing signals necessary for the station node to operate within this circuit are created based on the clock components extracted by REP.

The data component enters the line switching circuit LSW,
Import data from the line specified in SV. The synchronization flag detection circuit SYNC detects the synchronization flag in the frame header. The timing signal from the TIM becomes valid when synchronization is established. The data selected by the line switching circuit enters a register S/P REG for converting serial data into parallel data and is converted into parallel data. Parallel data passes through buffer registers REG#0 to 2, multiplexer MPX for switching out data, and P/S for converting parallel data to serial data.
It is sent out to the transmission line via the REG repeater.

R-BUFFER, S-BUFFER, CH CONT,
ADR/COMP is used when exchanging data between CPUs or I/Os. An address is added to the data area in the frame, the address is compared with the address set in the address setting comparison circuit ADR/COMP, and if they match, the received data is transferred to the common control unit.
Loaded into the reception buffer circuit R BUFFER under the control of COMMON CONT. The data in the reception buffer is sent to the CPU or I/O according to a certain procedure under the control of the channel control circuit CH CONT. Data from the CPU or I/O is sent to the transmission buffer circuit S BUFFER according to a certain transmission control procedure under the control of the channel control circuit.
After being stored once in the memory, it is sent out onto the transmission line via MPX, P/S REG, and REP under the control of the common control circuit. The data sent out on the transmission path is received by another station node using the method described above.

The error register ERR REG stores various error information, and when instructed by the SV, that is, the node address (NADR) in the frame header.
When the address matches the address set in the address setting circuit, error information is output under the control of the common control circuit.
Via MPX, P/S REG, REP, transmission line,
Notify highway monitoring equipment.

As mentioned above, the present invention allows even if a failure occurs on one side of a duplex transmission line, it can be
The SV polls all nodes connected to the transmission path, and the address of the failure detection node is learned from the response. Therefore, according to the present invention, even if a fault occurs in a remote location, the fault detection node can be identified at the location where the SV is installed, such as at the center, and system maintenance and operation operations can be facilitated. .

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of a data highway system according to an embodiment of the present invention, Figure 2 is the configuration of a data format frame flowing on a transmission path, Figure 3 is a detailed diagram of a frame header section, and Figure 4 is a diagram of an operation code section. Detailed view, FIG. 5 is an SV of an embodiment according to the present invention.
FIG. 6 is a block diagram of a station node according to an embodiment of the present invention. In Figure 1, SV is a highway monitoring device;
ST is a station node, L is a transmission line, CPU is a processing unit, and IO is an input/output device.

Claims (1)

[Claims] 1 One highway monitoring device and a plurality of station nodes are connected to a duplicated circular transmission path, and each station node extracts a clock signal from a data format frame sent from the highway monitoring device, and In a data highway system in which data transmission and reception is controlled based on signals and communication is performed between any of the station nodes and between the highway monitoring device and the station node, when an out-of-synchronization occurs in the transmission path or the station node, In addition to reconfiguring the transmission path using the backup system, when normal single-system operation becomes possible, the highway monitoring device uses a specific area within the data format frame flowing on the normal transmission path. Then, polling is performed individually on all the station nodes connected to the transmission path, collects synchronization error information from all the station nodes that remember that the synchronization has occurred, and updates the synchronization. A data highway method characterized in that a location where a synchronization error occurs is identified based on the continuity of the number of the station node that sent the error information and the data transmission direction at the time of synchronization loss.