JPS642108U - - Google Patents
Info
- Publication number
- JPS642108U JPS642108U JP9643287U JP9643287U JPS642108U JP S642108 U JPS642108 U JP S642108U JP 9643287 U JP9643287 U JP 9643287U JP 9643287 U JP9643287 U JP 9643287U JP S642108 U JPS642108 U JP S642108U
- Authority
- JP
- Japan
- Prior art keywords
- data
- circuit
- comparison reference
- minimum value
- maximum value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 10
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 2
- 238000006243 chemical reaction Methods 0.000 claims 5
- 238000005259 measurement Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Analogue/Digital Conversion (AREA)
- Measurement Of Current Or Voltage (AREA)
Description
添付図面はいずれもこの考案の実施例に係り、
第１図は測定装置本体に組み込まれた最大値／最
小値検出回路の構成を示すブロツク線図、第２図
はその要部の詳細を示す回路図、第３図Ａ及び第
３図Ｂはそれぞれ最大値検出及び最小値検出にお
けるデータ入れ替えの経過説明図である。
図中、１は測定装置本体、２は信号源、３はＡ
／Ｄコンバータ、４は測定部、１０は最大値／最
小値検出回路、１１は比較基準データ出力回路、
１２はコンパレータ、１３はフリツプフロツプ回
路、１４はラツチ信号発生回路、１５は桁制御回
路、１６はデータラツチ回路、Ｓ１ないしＳ３は
スイツチ、Ｇ３ないしＧ０はレジスタである。
All attached drawings relate to embodiments of this invention.
Figure 1 is a block diagram showing the configuration of the maximum/minimum value detection circuit built into the main body of the measuring device, Figure 2 is a circuit diagram showing details of its main parts, and Figures 3A and 3B are FIG. 7 is an explanatory diagram of the progress of data replacement in maximum value detection and minimum value detection, respectively. In the figure, 1 is the measuring device main body, 2 is the signal source, and 3 is A
/D converter, 4 is a measuring section, 10 is a maximum value/minimum value detection circuit, 11 is a comparison reference data output circuit,
12 is a comparator, 13 is a flip-flop circuit, 14 is a latch signal generation circuit, 15 is a digit control circuit, 16 is a data latch circuit, S1 to S3 are switches, and G3 to G0 are registers.
Claims (1)
ル変換し測定部にて所定の測定を行うとともに、
上記デイジタル変換データから上記被測定信号の
最大値もしくは最小値を上記測定と並行的に検出
する測定器の最大値／最小値検出回路において、 該最大値／最小値検出回路は、最大値検出もし
くは最小値検出の選択スイツチとゲート素子とを
含み、上記スイツチの選択動作に応じ上記ゲート
素子にて所定の初期比較基準データを形成して送
出するとともに、上記被測定信号のデイジタル変
換データをその後の比較基準データとして上記ゲ
ート素子より送出する比較基準データ出力回路と
、 上記デイジタル変換データの桁数に対応するレ
ジスタを有し、上記比較基準データ出力回路から
の比較基準データをそれぞれ上記対応するレジス
タに一時的に保持するデータラツチ回路と、 該データラツチ回路から与えられる比較基準デ
ータと上記Ａ／Ｄコンバータから加えられるデイ
ジタル変換データとの大小、又は一致をその上位
桁から下位桁へ向けて順次比較するコンパレータ
と、 フリツプフロツプ回路とラツチ信号発生回路と
からなり、上記コンパレータの大小比較出力に関
連して上記データラツチ回路の対応するレジスタ
へラツチ信号を発し、該レジスタに保持されてい
る比較基準データをそれぞれ最大値検出又は最小
値検出に応じて上記デイジタル変換データ中のよ
り大なるデータ、もしくはより小なるデータと入
れ替え保持させる桁制御回路とを備えていること
を特徴とする測定器の最大値／最小値検出回路。[Claims for Utility Model Registration] The signal to be measured is digitally converted by an A/D converter and a predetermined measurement is performed by a measuring section, and
In a maximum value/minimum value detection circuit of a measuring instrument that detects the maximum value or minimum value of the signal under test from the digital conversion data in parallel with the measurement, the maximum value/minimum value detection circuit detects the maximum value or It includes a minimum value detection selection switch and a gate element, and in response to the selection operation of the switch, the gate element forms and sends out predetermined initial comparison reference data, and the digital conversion data of the signal under test is subsequently It has a comparison reference data output circuit that sends out from the gate element as comparison reference data, and a register corresponding to the number of digits of the digital conversion data, and the comparison reference data from the comparison reference data output circuit is sent to the corresponding register. a data latch circuit that temporarily holds data, and a comparator that sequentially compares the comparison reference data given from the data latch circuit and the digital conversion data added from the A/D converter for magnitude or coincidence from the upper digits to the lower digits. The circuit includes a flip-flop circuit and a latch signal generation circuit, which issues a latch signal to the corresponding register of the data latch circuit in relation to the magnitude comparison output of the comparator, and sets the comparison reference data held in the register to the respective maximum value. Maximum value/minimum value detection of a measuring instrument characterized by comprising a digit control circuit that replaces and holds larger data or smaller data in the digital conversion data according to detection or minimum value detection. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987096432U JPH0517604Y2 (en) | 1987-06-23 | 1987-06-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987096432U JPH0517604Y2 (en) | 1987-06-23 | 1987-06-23 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS642108U true JPS642108U (en) | 1989-01-09 |
| JPH0517604Y2 JPH0517604Y2 (en) | 1993-05-12 |
Family
ID=30962171
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987096432U Expired - Lifetime JPH0517604Y2 (en) | 1987-06-23 | 1987-06-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0517604Y2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52102752A (en) * | 1976-02-25 | 1977-08-29 | Gen Corp | Holding circuit for maximum or minimum value of input analogue signal |
| JPS5313346A (en) * | 1976-07-21 | 1978-02-06 | Mitsubishi Electric Corp | Maximum value counter |
| JPS60104942U (en) * | 1983-12-19 | 1985-07-17 | 三菱電機株式会社 | Maximum or minimum value detection device |
-
1987
- 1987-06-23 JP JP1987096432U patent/JPH0517604Y2/ja not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52102752A (en) * | 1976-02-25 | 1977-08-29 | Gen Corp | Holding circuit for maximum or minimum value of input analogue signal |
| JPS5313346A (en) * | 1976-07-21 | 1978-02-06 | Mitsubishi Electric Corp | Maximum value counter |
| JPS60104942U (en) * | 1983-12-19 | 1985-07-17 | 三菱電機株式会社 | Maximum or minimum value detection device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0517604Y2 (en) | 1993-05-12 |
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