JPS6421941A - Multilayer gate array - Google Patents

Multilayer gate array

Info

Publication number
JPS6421941A
JPS6421941A JP62177562A JP17756287A JPS6421941A JP S6421941 A JPS6421941 A JP S6421941A JP 62177562 A JP62177562 A JP 62177562A JP 17756287 A JP17756287 A JP 17756287A JP S6421941 A JPS6421941 A JP S6421941A
Authority
JP
Japan
Prior art keywords
region lines
vertical direction
chip
wiring
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62177562A
Other languages
Japanese (ja)
Inventor
Kazushige Shibuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP62177562A priority Critical patent/JPS6421941A/en
Publication of JPS6421941A publication Critical patent/JPS6421941A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To increase the number of gates in one chip without enlarging an area, by laminating a plurality of layers, on each of which transistor region lines and wiring region lines are alternately aligned, in the vertical direction. CONSTITUTION:A plurality of layers 101-103 are laminated in the vertical direction. On each layer, transistor region lines 104 and wiring region lines 105 are alternately aligned in the horizontal direction. On the odd-numbered layer and the even-numbered layer for the transistor region lines 104 and the wiring region lines 105, the transistor region lines 104 and the wiring region lines 105 are arranged so that they are not overlapped at the same positions with respect to the vertical direction. Since the integration density of the number of gates in one chip is increased in this way, the area of the chip can be reduced. Therefore, the wiring length can be shortened, and the speed in the circuit can be increased. The mutual effects of the transistor regions between the upper and lower layers can be reduced, and the element density with respect to the vertical direction can be made high.
JP62177562A 1987-07-16 1987-07-16 Multilayer gate array Pending JPS6421941A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62177562A JPS6421941A (en) 1987-07-16 1987-07-16 Multilayer gate array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62177562A JPS6421941A (en) 1987-07-16 1987-07-16 Multilayer gate array

Publications (1)

Publication Number Publication Date
JPS6421941A true JPS6421941A (en) 1989-01-25

Family

ID=16033135

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62177562A Pending JPS6421941A (en) 1987-07-16 1987-07-16 Multilayer gate array

Country Status (1)

Country Link
JP (1) JPS6421941A (en)

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