JPS6421964A - Hetero-bipolar transistor - Google Patents

Hetero-bipolar transistor

Info

Publication number
JPS6421964A
JPS6421964A JP62179347A JP17934787A JPS6421964A JP S6421964 A JPS6421964 A JP S6421964A JP 62179347 A JP62179347 A JP 62179347A JP 17934787 A JP17934787 A JP 17934787A JP S6421964 A JPS6421964 A JP S6421964A
Authority
JP
Japan
Prior art keywords
semiconductor layer
groove
layer
conductivity type
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62179347A
Other languages
Japanese (ja)
Inventor
Etsuji Omura
Tetsuo Shiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62179347A priority Critical patent/JPS6421964A/en
Publication of JPS6421964A publication Critical patent/JPS6421964A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To manufacture an HBT with flat surface easily integrated by a method wherein the first conductivity type the first semiconductor layer, the second conductivity type the second semiconductor layer and the first conductivity type the third semiconductor layer are successively formed along the wall surface inside a groove cut in a semiconductor substrate to fill the groove. CONSTITUTION:A semiconductor substrate 1 with a groove 3 cut therein, the first conductivity type the first semiconductor layer 4, the second conductivity type the second semiconductor layer 5 and the first conductivity type the third semiconductor layer 6 successivly formed along the wall surface inside the groove 3 to be filled are provided. At this time, the forbidden band width of the first semiconductor layer 4 or the third semiconductor layer 6 is made wider than that of the second layer 5. For example, the groove 3 is cut in the semiinsulating GaAs substrate 1 and then the collector layer 4 as the first semiconductor layer comprising n<->AlGaAs, the base layer 5 as the second semiconductor layer comprising p<->GaAs, the emitter layer 6 in wider forbidden width as the third semiconductor layer comprising n<+>AlGaAs and a p<+>region 7 to lead-out an electrode from the thin base layer 5 are formed inside the groove 3.
JP62179347A 1987-07-16 1987-07-16 Hetero-bipolar transistor Pending JPS6421964A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62179347A JPS6421964A (en) 1987-07-16 1987-07-16 Hetero-bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62179347A JPS6421964A (en) 1987-07-16 1987-07-16 Hetero-bipolar transistor

Publications (1)

Publication Number Publication Date
JPS6421964A true JPS6421964A (en) 1989-01-25

Family

ID=16064254

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62179347A Pending JPS6421964A (en) 1987-07-16 1987-07-16 Hetero-bipolar transistor

Country Status (1)

Country Link
JP (1) JPS6421964A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0464301U (en) * 1990-10-16 1992-06-02
DE10152087A1 (en) * 2001-10-23 2003-05-08 Infineon Technologies Ag Production of substrate used in the manufacture of semiconductor structure especially HBT cell comprises structuring substrate to form recess in the surface, growing a layer sequence, and planarizing the substrate and/or the layer sequence

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0464301U (en) * 1990-10-16 1992-06-02
DE10152087A1 (en) * 2001-10-23 2003-05-08 Infineon Technologies Ag Production of substrate used in the manufacture of semiconductor structure especially HBT cell comprises structuring substrate to form recess in the surface, growing a layer sequence, and planarizing the substrate and/or the layer sequence

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