JPS6422050U - - Google Patents

Info

Publication number
JPS6422050U
JPS6422050U JP1987116913U JP11691387U JPS6422050U JP S6422050 U JPS6422050 U JP S6422050U JP 1987116913 U JP1987116913 U JP 1987116913U JP 11691387 U JP11691387 U JP 11691387U JP S6422050 U JPS6422050 U JP S6422050U
Authority
JP
Japan
Prior art keywords
pellet
bonded
pellets
package
pasted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987116913U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987116913U priority Critical patent/JPS6422050U/ja
Publication of JPS6422050U publication Critical patent/JPS6422050U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages

Landscapes

  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図Ａは本考案の一実施例の縦断面図、第１
図Ｂはその配線図、第２図Ａは本考案の他の実施
例の縦断面図、第２図Ｂはその配線図、第３図は
、従来パツケージの縦断面図である。ａ及びｂは
リードフレーム、ｃ及びｄはペレツト、ｅはモー
ルド樹脂、ｆはボンデイング線。 FIG. 1A is a vertical sectional view of one embodiment of the present invention;
FIG. 2B is a wiring diagram thereof, FIG. 2A is a longitudinal sectional view of another embodiment of the present invention, FIG. 2B is a wiring diagram thereof, and FIG. 3 is a longitudinal sectional view of a conventional package. a and b are lead frames, c and d are pellets, e is mold resin, and f is bonding wire.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ボンデイングパツドが左右対象である２つのペ
レツトと裏表両面にマウント・ボンデイングでき
るリードフレームを有し、一方のペレツトを裏側
、他方のペレツトを表側にマウント・ボンデイン
グし、貼り合せ、１つのパツケージに封入するこ
とを特徴とする集積回路装置。 The bonding pad has two symmetrical pellets and a lead frame that can be mounted and bonded on both the front and back sides.One pellet is mounted and bonded on the back side and the other pellet on the front side, and the pellets are pasted and sealed in one package. An integrated circuit device characterized by:
JP1987116913U 1987-07-29 1987-07-29 Pending JPS6422050U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987116913U JPS6422050U (en) 1987-07-29 1987-07-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987116913U JPS6422050U (en) 1987-07-29 1987-07-29

Publications (1)

Publication Number Publication Date
JPS6422050U true JPS6422050U (en) 1989-02-03

Family

ID=31359886

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987116913U Pending JPS6422050U (en) 1987-07-29 1987-07-29

Country Status (1)

Country Link
JP (1) JPS6422050U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991014282A1 (en) * 1990-03-15 1991-09-19 Fujitsu Limited Semiconductor device having a plurality of chips

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1991014282A1 (en) * 1990-03-15 1991-09-19 Fujitsu Limited Semiconductor device having a plurality of chips

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