JPS642244B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital filter, and more particularly, it sequentially reads numerical table outputs from an accumulator using vectors corresponding to each bit of a sample value, and accumulates the values. This invention relates to a digital filter that obtains a filter output by calculation.

According to theory, in general, in a digital filter, when the input sequence is a discrete signal (sample value) x(nT) obtained by sampling a continuous signal x(t) at an interval of T (seconds), the output The series y(nT) is: y(nT)= _K 〓 ^K=0 a _k x {(n-k)T}+ _L 〓 ^l=1 b _l y{(n-l)T} ...(1) It is obtained from a constant coefficient linear difference equation, and is also a sample value. Equation (1) represents a cyclic digital filter when at least one b _l is not zero, and represents an acyclic digital filter when all b _l are zero. For convenience, equation (1) is written as y _o = _K 〓 ^K=0 a _k x _ok + _L 〓 ^l=1 b _l y _ol ……(2). However, x _ok △ = x {(n-k)T}
(k=0, 1, ..., K), y _ol △ = y {(n-l)
T} (l=0, 1, ..., L). Furthermore, equation (2) can be formally expressed as Y= _N-1 〓 ⁱ⁼⁰ α _i Z _i ……(3). However, Y is y _o , α _i is a _k or
b _l and Z _i represent x _ok or y _ol , respectively.

If the expression (3) is used as is, N multiplications and (N-1) additions must be performed to obtain the filter output Y at one sampling point.
When handling digitally, since these multiplications and additions are binary operations, it takes time to obtain the output Y, and the circuit configuration becomes very complicated because a multiplier must be provided.

One of the features of digital filters is that so-called time division multiplexing is possible, in which one piece of hardware can equivalently operate as a plurality (R) of filters. In order to operate as R filters, the multiplication and addition must be completed within the time T/R, but in reality, the multiplicity R cannot be increased because the calculation time is long. Also, a simple substance (R=
Even when used as a filter in 1), the sampling period T cannot be made small due to the long computation time, so the frequency that can be handled cannot be made high.

For this reason, there are several known methods to obtain the filter output value of equation (3) without using a binary multiplier. Peled, A. and Liu, B.: “A new
“hardware realization of digital filters”
IEEE Trans. Acoust., Speech & Signal
Process., ASSP-22, 6, p. 456 (1974) and Digital Filter by Alain Croisier et al. These are explained below.

First, the first one (IEEE Trans.ASSP-22) will be described. The sample value Z _i in equation (3) is expressed as a binary number when handled digitally, but since it can take both positive and negative numbers (it can take both positive and negative numbers), it can be expressed as a binary number that includes positive and negative numbers. is expressed in complement code. That is, Z _i is a two's complement code sample value. Using this representation method, the size of Z _i where the data word length is expressed in M bits is as follows (To simplify the explanation, we will consider only integers, but the following explanation will of course be based on decimal numbers. (applicable as well).

Z _i =−Z _i ^M 2 ^M-1 + _M-1 〓 ^J=1 Z _i ^j 2 ^j-1 ...(4) However, Z _i ^j is 0 or 1. From equation (4), Z _i ^M
When Z i is 0, Z _i is a positive number, and when Z _i ^M is 1, Z _i
Since it can be seen that is a negative number, it can be seen that Z _i ^M is a bit representing polarity.

Substituting equation (4) into equation (3), Y= _N-1 〓 ⁱ⁼⁰ α _i (−Z _i ^M 2 ^M-1 + _M-1 〓 ^J=1 Z _i ^j 2 ^j-1 )=− 2 ^M-1 _N-1 〓 ⁱ⁼⁰ α _i Z _i ^M + _M-1 〓 ^J=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i Z _i ^j ...(5), so the number The table output ψ ^j and the function ψ are ψ ^j △ = ψ (Z ₀ ^j , Z ₁ ^j , ..., Z _N-1 ^j )△ = _N-1 〓 ⁱ⁼⁰ α _i Z _i ^j ......(6) Then, equation (5) becomes Y=−ψ(Z ₀ ^M , Z ₁ ^M , ..., Z _N-1 ^M )2 ^M-1 + _M-1 〓 ^J=1 ψ(Z ₀ ^j , Z ₁ ^j , ..., Z _N-1 ^j )2 ^j-1 = −ψ ^M 2 ^M-1 + _M-1 〓 ^J=1 ψ ^j 2 ^j-1 ...(7)

The function ψ of equation (6) is the N variables Z ₀ ^j , Z ₁ ^j ,...
..., Z _N-1 ^j can take on 2 ^N values depending on whether each j is 0 or 1. Therefore, ψ ^j in equation (6) is N variables.
A set of Z ₀ ^j , Z ₁ ^j , ..., Z _N-1 ^j , that is, an N-dimensional vector (Z ₀ ^j , Z ₁ ^j , ..., Z _N-1 ^j ) as an address value, 2 ^N can be retrieved from a storage device such as read-only memory (ROM) or random access memory (RAM) in which the value of ψ of is stored. Therefore, by repeating (M-1) times the operation of sequentially sisting and adding ψ ^j extracted from equation (7) in this way, and shifting and calculating the extracted ψ ^M at the Mth time, the filter output Y is calculated. I understand that you are required to do so. A configuration based on this method is shown in FIG. In Figure 1, N=5 in equation (3), α _i =a _i (i=0,
1, 2), α ₃ = b ₁ and α ₄ = b ₂ , and Z _i = x _o-1 (i =
0, 1, 2), Z ₃ = y _o-1 , Z ₄ = y _o-2 and Y = y _o
y _o = a ₀ x _o + a ₁ x _o-1 + a ₂ x _o-2 + b ₁ y _o-1 + b ₂ y _o-2
...(8) shows the configuration of a second-order cyclic digital filter. At this time, the functions ψ ^j and ψ are calculated from equation (6) as ψ ^j = ψ (x _o ^j , x _o-1 ^j , x _o-2 ^j , y _o-1 ^j , y _o-2 ^j ) = a ₀ x _o ^j +a ₁ x _o-1 ^j +a _2o-2 ^j +b _{1 y o-} 1 ^j +b ₂ y _o-2 ^j
...(9), and the filter output y _o is obtained from equation (7) as follows: y _o =-ψ ^M 2 ^M-1 + _M-1 〓 ^J=1 ψ ^j 2 ^j-1 ...(10).

In Figure 1, SR1 to SR3 are serial type shift registers, PSR is a parallel input-serial output type shift register, R1 and R2 are registers, and MEM1 is a serial type shift register.
is a storage device such as ROM or RAM, ADS is an adder capable of subtraction, and ACC1 consists of ADS and R2, and the output line of R2 is connected to one input of ADS with one bit shifted toward the lower bit, that is, R2 It is an accumulator in which the lower two bits of ADS are connected to the lower first bit of ADS, and is constructed as shown in the figure. In the figure, the sample value
Each bit of _xo is sequentially applied to the shift register SR1 in series starting with the least significant bit. Also at the same time
Each bit of x _o-1 is also sequentially moved from the least significant bit to shift register SR1 to SR2,
Each bit of x _o-2 comes out sequentially from SR2. _xo ,
Each bit of x _o-1 and x _o-2 is sequentially applied to storage device MEM1. Similarly, each bit of yo _-1 stored in parallel in shift register PSR sequentially enters shift register SR3, and each bit of yo _-2 sequentially comes out from SR3. y _o-1 and
Each bit of y _o-2 is sequentially stored in the storage device MEM1.
given to. Therefore, the storage device MEM1 contains 5 bits of information x _o ^j , x _o-1 ^j , x _o-2 ^j , y _o-1 ^j , y _o-2 ^j
is given. Storage device as shown in Figure 1
MEM1 has the above 5 bits as the address value32
There are memory locations, each of which has data as equation (9).
The value of ψ previously calculated by is stored in a B-bit two's complement code. Therefore, given a five-dimensional vector (x _o ^j , x _o-1 ^j , x _o-2 ^j , y _o-1
^j , yo _-2 ^j ) allows ψ ^j to be extracted, which is stored in register R1. Next, the output of register R1 is given to adder ADS in storage device ACC1, and the partial sum Ψ ^j = _j-1 〓 ^j=1 ψ ^j 2 ^j-1 (before adder ADS) stored in register R2 is (this operation is called shift addition).

Next, the new vector (x _o ^j
+1 , x _o-1 ^j+1 , x _o-2 ^j+1 , y _o-1 ^j+1 , y _o-2 ^j+1 ) are given, and the corresponding ψ ^j+1 is extracted. . This is shifted and added to the partial sum _j 〓 ^j=1 ψ ^j 2 ^j-1 stored in the register R2 by the adder ADS through the register R1 again. This operation is repeated (M-1) times, and at the Mth time, the partial sum obtained by shifting and adding (M-1) times stored in register R2 is _M-1 〓 ^J=1 ψ ^j
2 ^j-1 shifted by 1 bit, ψ extracted from the storage device MM1 by the vector (x _o ^M , x _o-1 ^M , x _o-2 ^M , y _o-1 ^M , y _o-2 ^M ) By subtracting ^M by the adder ADS through the register R1, y _o in equation (10) can be obtained.

Although this example has a simpler circuit configuration and faster calculation time than the method using a binary multiplier described above, the circuit configuration and control are still complex because the adder must also be capable of subtraction. It has the disadvantage of being.

For this reason, the second conventional example (Special Publication No. 53-30972)
We will explain how to obtain the filter output using only addition. The sample value Z _i is expressed as a binary number in the form Z _i = _M 〓 ^j=1 Z _i ^j 2 ^j-1 (11). However, Z _i is 0
or 1.

Substituting equation (11) into equation (3), Y= _N-1 〓 ⁱ⁼⁰ α _iM 〓 ^j=1 Z _i ^j 2 ^j-1 = _M 〓 ^j=1 2 ^j-1 _N-1 〓 ^{i= 0} α _i Z _i ^j ...(12) Therefore, if the functions ψ ^j and ψ are defined by equation (6), equation (12) becomes Y= _M 〓 ^j=1 ψ (Z ₀ ^j , Z ₁ ^j , ..., Z _o-1 ^j )2 ^j-1 = _M 〓 ^j=1 ψ ^j 2 ^j-1 ...(13) It is expressed as: only addition, not subtraction. Therefore, Equation (13) indicates that filter output Y can be obtained by sequentially repeating shift and addition of ψ ^j M times.

In this example, since there is no need to include subtraction in the adder, the circuit configuration and control are also simplified. However, for this example to operate as a filter, () As is clear from equation (11), Z _i must be non-negative (positive or zero) (restrictions are imposed on the signals that can be used). In the case of a cyclic filter, Z _i is only the input sample value, so it is sufficient if the input sample value is non-negative, but in the case of a cyclic filter, Z _i includes not only the input sample value but also the output sample value.
Z _i must be non-negative and Y must be non-negative at the same time. That is, it is limited to the necessity of α _i such that the impulse response is non-negative, and filter operation is not possible in other cases.

Therefore, this example is applicable only in extremely limited cases. Further, a desirable requirement for a practical filter is that the digital signal (sample value) is a signal that can take on both positive and negative numbers (both positive and negative signs) similarly to analog signals. Filtering only positive signals also increases the overflow of the filter output.

An object of the present invention is to improve the drawbacks of the above-mentioned prior art, and to be usable for signals of both positive and negative signs.
Another object of the present invention is to provide a digital filter using only addition operations.

The most basic feature of the present invention is that the first term representing subtraction on the right side of the second equation of equation (5) is the variable Z ₀ ^M ,
Focusing on the fact that Z ₁ ^M , ..., Z _o-1 ^M is a function, the first term is converted to a constant, and the constant is stored in the storage device and retrieved, so that the filter output can be simply added. It is calculated using the following calculation. The present invention will be explained in detail below.

Since the sample value Z _i is a signal with both positive and negative signs, it can be expressed using the aforementioned two's complement code as Z _i =−Z _i ^M 2 ^M-1 + _M-1 〓 ^J=1 Z _i ^{j 2 j-1} ……( 4). As mentioned above, substituting equation (4) into equation (3) yields equation
(5) is derived.

Y=−2 ^M-1 _N-1 〓 ⁱ⁼⁰ α _i Σ _i ^M + _M-1 〓 ^J=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i Zz _i ^j ……(5) By the way, What should be noted is that Z _i ^j + _i ^j =1 (14) holds true. However, _i ^j is Z _i
represents the negation of ^j . That is, when Z _i ^j =0, _i ^j =
1, and when Z _i ^j =1, _i ^j =0.

From equation (14), Z _i ^j =1- _i ^j , so substituting it into the second term of equation (5) yields Y=-2 ^M-1 _N-1 〓 ⁱ⁼⁰ α _i Z _i ^M + _{M- 1} 〓 ^J=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i (1− _i ^j )＝ _M-1 〓 ^J=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i − _M 〓 ^{j= 1} 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _{i i} ^j ...(15) However, it is defined as _i ^M △ = Z _i ^M ……(16). Equation (16) shows that the polarity bit of Z _i expressed in two's complement code is formally regarded as its inverted _i ^M .

Therefore, the functions ψ ₁ ^j , ψ ₁ and the constant ψ _I ^M+1 are respectively ψ _I ^j △ = ψ _I ( ₀ ^j , _I ^j , ..., _N-1 ^j ) △ = − _N-1 〓 ^{i =0} α _{i i} ^j
...(17) ψ ₁ ^M+1 △ =2 ^-M _M-1 〓 ^J=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i = 2 ^-M (2 ^M-1 −1) _N-1 〓 ⁱ⁼⁰ α _i ...(18) If defined as, Equation (15) becomes Y=ψ _I ^M+1 2 ^M + 〓 ^j=1M ψ _I ^j 2 ^j-1 = _M+1 〓 ^j=1 ψ _I ^j 2 ^j-1 ...(19) By the way, equation (18) can be approximated as follows when the word length M of Z _i is sufficiently large: ψ ₁ ^M+1 (1/2) _N-1 〓 ⁱ⁼⁰ α _i △ = A (constant) ... (18') It is expressed as Furthermore, equation (19) is expressed as Y=[ψ _I ^M+1 +[ψ _I ^M +…+[ψ _I ^j +…+{ψ _I ³ + (ψ
_I ² +ψ _I ¹ 2 ^-1 )2 ^-1 }2 ^-1 …〕2 ^-1 …〕2 ^-1 〕2 ^M …(20) It is also expressed as: Here, the partial sum Ψ ^j is Ψ ^j △ Ψ ^j △ = ψ _I ^j + [ψ _I ^j-1 +……+{φ _I ³ + ψ _I ² + ψ _I ¹ 2 ^-1 ) 2 ^-1
}2 ^-1 ...]2 ^-1 ...(21) If we define Ψ ^j = ψ _I ^j + Ψ ^j-1 2 ^-1 ... (22) holds. However, it is assumed that Ψ ⁰ △ =0.

From equation (21), equation (20) can be expressed as Y=Ψ ^M+1 2 ^M (23).

In addition, if we use the identity Z _i ^M + _i ^M = 1 ... (14') instead of equation (14) and substitute Z _i ^M = 1 - _i ^M into equation (5), equation (15) becomes Y=−2 ^M-1 _N-1 〓 ⁱ⁼⁰ α _i + _M 〓 ^j=1 2 ^j-1 _N-1 〓 ⁱ⁼⁰ α _i Z _i ^j ……(15′). However, it is defined as Z _i ^M △ = _i ^M ……(16′). At this time, ψ _I ^j △ = ψ _I ( ₀ ^j , ₁ ^j , ..., _N-1 ^j ) △ = _N-1 〓 ⁱ⁼⁰ α _i Z _i ^j
…(17′) ψ _I ^M+1 △ =−(1/2) _N-1 〓 ⁱ⁼⁰ α _i (constant) …(18″) If we define Equation (16′) and Equation (15′ ) are respectively Y=ψ _I ^M+1 2 ^M + _M 〓 ^j=1 ψ _i ^j 2 ^j-1 = _M+1 〓 ^j=1 ψ _i ^j 2 ^j-1 ...(19), and the above equation (16) and is exactly the same as equation (19). Therefore, the first and second embodiments described below are the same in this case as well. The present invention
Equations (16), (17) {(17′)}, (18) {(18″)},
(19) or equation (16), (17) {(17′)}, (18) {(18″)
},
Based on the calculation principles of (22) and (23), the following structure is the gist.

That is, in a digital filter that filters M-bit two's complement code sample values (binary code sample values) Z _i containing N positive and negative values that arrive successively, and outputs a filter output expressed by a predetermined function. , receives the binary code sample value Z _i , inverts all bits except the bit indicating the polarity of the received binary code sample value Z _i by an inverting means, and the inverted sample value _i = _i ^M _i ^M …… _i ²
N pieces of _i ¹ (i=0, 1, . . . , N-1) are prepared, and an N-dimensional vector ( ₀ ^j , ₁ ^j , . . . , _o-1 ^j ) is generated by a vector generating means.

In short, the vector generating means sequentially generates and outputs N bit information corresponding to each bit of the N inverted binary code sample values. The N-bit information sequentially generated and outputted by this vector generating means is input to a vector detecting means for detecting that the information is a predetermined vector at times other than the (M+1)th time.

The detection output from this vector detection means is processed by an accumulator using a predetermined formula associated with a coefficient α _i and a function ψ determined by the N-bit information. The coefficient α _i and the function ψ are stored in the storage device together with the constant value A used in the predetermined formula. In this storage device, the constant value A is stored at a predetermined address, and the coefficient α _i and the function ψ determined by the N-bit information are stored at other addresses. From this storage device
Vectors excluding zero-dimensional vectors ( ₀ ^j , ₁ ^j , …
…, ^n-1j ) is used as the address value to extract the output ψ ₁ ^j . The output ψ ₁ ^j is added to the shift adder (accumulator), that is, zero for the address value of the zero vector (since the value of ψ ₁ ^j for the zero vector is zero). After repeating this operation M times, the constant value A is extracted from the accumulator and added to the accumulator at the (M+1)th time.

In addition to the above, the N-bit information is received and 1≦j
For M times where ≦M, an address storing (accumulating) the function ψ corresponding to the bit information is generated,
Address generation means is provided for generating the predetermined address at the (M+1)th time. In this way, the filter output Y according to equation (19) or equation (23) is obtained. That is, the filter output Y for the original sample value Z _i of both positive and negative signs is determined by the operation of addition only.

Next, the present invention will be specifically described with reference to embodiments shown in the drawings. It should be noted that both the embodiments shown in FIGS. 2 and 3 are configured for the second-order cyclic digital filter expressed by equation (8), as in the case of FIG. 1 for simplicity and comparison. It is something. At this time, the functions ψ _I ^j and ψ _I are expressed by equation (17)
From ψ _I ^j = ψ _I ( _o ^j , _o-1 ^j , _o-2 ^j , _o-1 ^j , _o-2 ^j ) = − (a ₀ ^nj + a _{1 o-1} ^j + a _{2 o-2} ^j + b _{1 o-1} ^j +b _{2 o-2} ^j ) ...(24), and the constant φ _I ^M+1 is calculated from equation (18) or equation (18') as φ _I ^M+1 = A=2 ^-M ( 2 ^M-1 −1) (a ₀ +a ₁ +a ₂ +b ₁ +b ₂ )
(1/2 (a ₀ + a ₁ + a ₂ + b ₁ + b ₂ )...(25).Equation (19) and expression (23) are equivalent, so for the sake of explaining the operation, expression (23) is used for filtering. output
y _o becomes y _o =Ψ ^M+1 2 ^M ……(26).

The first embodiment will be explained with reference to FIG.

In Figure 2, EOR1 and EOR2 are exclusive OR, SR1 to SR3 are serial shift registers,
PSR is a parallel input-serial output type shift register.
NOT is negation, OR is logical sum, AND1 to AND5 is logical product, MEM2 is a storage device such as ROM or RAM, R1 and R2 are registers, AD is adder,
ACC2 consists of AD and R2, and like ACC1, it is an accumulator that shifts the output of R2 by one bit in the direction of the lower bit and is connected to the input of AD, and is constructed as shown in the figure. In Figure 2, each bit of the sample value _xo is applied to EOR1 in series starting from the least significant bit, and the polarity bit is removed by setting the signal _LM to high level at times other than the polarity bit passing time. All bits are inverted, and all bits except the polarity bit of _xo are inverted and provided to the shift register SR1 as a sample value _o . At the same time, each bit of the input sample value _o-1 delayed by 1 sample time is sequentially moved from shift register SR1 to SR2, and from SR2 the input sample value delayed by 2 sample times is transferred from shift register SR1 to SR2.
Each bit of x _o-2 comes out sequentially. _o , _o-1 and
Each bit of x _o-2 is sequentially ANDed AND1~
It is applied to the storage device MEM2 through AND3 and to the logical sum OR. Similarly, each bit of the output sample value y _o-1 delayed by one sample time stored in the shift register PSR in parallel is sequentially connected to an exclusive circuit for inverting all bits except the polarity bit as described above. Through logical sum EOR2
All bits except the polarity bit of y _o-1 are inverted and transferred to shift register SR3 as the sample value _o-1 , and from SR3 each bit of the output sample value _o-2 delayed by two sample times is sequentially transferred. come out. Each bit of _o-1 and _o-2 is sequentially connected to the storage device through AND4 and AND5, respectively.
MEM2, and is given to OR. Therefore, the storage device MEM2 contains 5 bits of information _o ^j ,
x _o-1 ^j , _o-2 ^j , _o-1 ^j , _o-2 ^j are given. As shown in FIG. 2, the storage device MEM2 has 32 storage locations whose address values are 5-bit information _o ^j , _o-1 ^j , _o-2 ^j , _o-1 ^j , _o-2 ^j . , and the value of ψ ₁ calculated in advance by equation (24) as data for each address value except the address value of the five-dimensional zero vector (0, 0, 0, 0, 0) is set to 2 of B bits. is stored in the complement code of As is clear from equation (24), the value of ψ ₁ is zero for a zero vector, so the value of the constant A calculated in advance by equation (25) is used as the address value of the zero vector. It is stored in two's complement code. When the given five-dimensional vector ( _o ^j , _o-1 ^j , _o-2 ^j , _o-1 ^j , _o-2 ^j ) is not equal to the zero vector, the storage device MEM2
ψ ₁ ^j is extracted from and stored in register R1.

During the first M operations, the signal H _M+1 is kept at low level, so the vector ( _o ^j , _o-1 ^j , _o-2
^j , _o-1 ^j , _o-2 ^j ) is equal to a zero vector, a roll bell signal is output from the logical OR as a result of detecting a zero vector, and this low level signal is supplied to register R1 as a clear signal, so the register Set the contents of R1 to zero.

Next, the output of the register R1 is given to the adder AD in the accumulator ACC2, and is shifted and added to the partial sum Ψ ^j-1 stored in the register R2 to obtain Ψ ^j .

Repeat this operation (M-1) times to obtain Ψ ^M-1
For the Mth time, the signal L _M is set to low level and the vector ( _o ^M , _o-1 ^M , o-2 M , _o-1 ^M , _{o- 2} ^M ) whose components are the polarity bits themselves that are not ^inverted is calculated. Perform the above operation to find Ψ ^M , and at the (M+1)th time, set the signal H _M+1 to high level and OR
By setting the output of , that is, the detection result of the zero vector, to high level, register R1 is not cleared, and a zero vector is generated from the logical products AND1 to AND5 by the low level signal generated from NOT, and the zero vector is The constant value A drawn from the storage device MEM2 as an address value is given to the adder AD through the register R1, and if it is shifted and added to the partial sum Ψ ^M stored in the register R2, Ψ ^M+1 , that is, equation (26) is obtained. The filter output y _o is determined.

Furthermore, in the first embodiment, the register R2 in the accumulator ACC2 may be replaced with a parallel input-parallel output type shift register.

Next, a second embodiment will be explained with reference to FIG.

Figure 3 is almost the same as Figure 2, but the difference is that instead of the accumulator ACC2 in Figure 2, register R2 is replaced with a parallel input-parallel output type shift register PPR. The point is that an accumulator ACC3 is provided.

Regarding the operation in FIG. 3, only the points different from those in FIG. 2 will be explained. When the given 5-dimensional vector ( ^j _o , ^j _o-1 , ^j _o-2 , ^j _o-1 , ^j _o-2 ) is equal to the zero vector, in Fig. 2, the output of the logical OR, that is, the zero The contents of register R1 are set to zero according to the vector detection result, and the contents of register R1 are
In contrast, in Figure 3, the output signal of the logical sum OR, that is, the signal as a result of the detection of the zero vector, is added to the adder AD.
It is supplied as a shift signal to the shift register PPR in ACC3, and the contents of the shift register PPR are changed to 1.
ψ ₁ ^j which becomes equivalently zero by bit shifting
is shifted and added.

Since the second embodiment is configured so that addition is not performed on zero vectors other than those occurring the (M+1)th time, the calculation time for obtaining the filter output y _o can be shortened.

Furthermore, in the second embodiment, the register R1 may be omitted and the storage device MEM2 and the accumulation device ACC3 may be directly connected.

In the first and second embodiments, the order of the components of the five-dimensional vector used as the address value to the storage device may be arbitrary. Accordingly, the contents of the storage device are made to correspond.

Also, 5-bit information _o ^j , _o-1 ^j , _o-2 ^j , _o-1
Of course, other means for generating ψ 1 ^j and _o-2 ^j and operations for reducing ψ ₁ ^j to zero equivalently to the zero vector can be considered. The constant ψ ₁ ^{M+1 is} stored in the memory location corresponding to the address value of the zero vector, but the vector ( _o ^j , _{o-1 j} ^, _o-2 ^j , _o-1 ^j , _{o -2} ^j ) may be stored in the memory location for the address value.

Furthermore, the address value is a five-dimensional vector ( _o ^j ,
x _o-1 ^j , _o-2 ^j , _o-1 ^j , _o-2 ^j ),
Generally 5 bits of information _o ^j , _o-1 ^j , _o-2 ^j , _o-1
^j , _o-2 ^j functions ( _o ^j , _o-1 ^j , _o-2 ^j , _o-1 ^j ,
_o-2 ^j
It can also be determined as an address value determined by

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a conventional digital filter using a subtractable adder, FIG. 2 is a diagram showing an embodiment of the present invention having a configuration that can be compared with the conventional example in FIG. The figure shows another embodiment of the invention. In the figure, ADS is a subtractable adder, AD is an adder, MEM1 and MEM2 are storage devices, and SR1 to
SR3 is a serial type shift register, PSR is a parallel input-serial output type shift register, R1 and R2 are registers, PPR is a parallel input-parallel output type shift register, EOR1 and EOR2 are exclusive OR,
AND1 to AND5 represent logical products, and ACC1 and ACC3 represent accumulation devices, respectively.

Claims (1)

[Claims] 1. Filter the M-bit binary code sample value Z _i containing N positive and negative values successively arriving, Y= _N-1 〓 ⁱ⁼⁰ α _i Z _i (where Z _i = −Z ^M _i 2 ^M-1 + _M-1 〓 ^J=1 Z _i ^j 2 ^j-1 ) In a digital filter that outputs a filter output Y expressed by a function, the binary code sample value is received. , inverting means for selectively inverting bits other than bits indicating polarity; vector generating means for sequentially outputting N bit information corresponding to each bit of the N inverted binary code sample values; Vector detection means for detecting that the N-bit information is a predetermined vector; and a storage device for accumulating a constant value A at a predetermined address and a coefficient α _i and a function ψ determined by the N-bit information at other addresses. and; receives the output ψ ^j of the storage device and the output of the vector detection means, and
When the bit information is not a predetermined vector, perform the accumulation ^j = ψ ^j+ Ψ ^j-1 2 ^-1 , and when the N bit information is a predetermined vector, perform the calculation Ψ ^j = Ψ ^j-1 2 ^-1 . an accumulator: receives the N-bit information, generates an address storing a function ψ corresponding to the N-bit information M times when 1≦j≦M, and generates the predetermined address at the M+1 time; What is claimed is: 1. A digital filter comprising an address generating means for generating an address.