JPS642455U - - Google Patents
Info
- Publication number
- JPS642455U JPS642455U JP9670787U JP9670787U JPS642455U JP S642455 U JPS642455 U JP S642455U JP 9670787 U JP9670787 U JP 9670787U JP 9670787 U JP9670787 U JP 9670787U JP S642455 U JPS642455 U JP S642455U
- Authority
- JP
- Japan
- Prior art keywords
- region
- drain region
- oxide film
- impurity concentration
- drift channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 1
Description
第１図〜第３図は本考案にかかる半導体装置の
一実施例の構成図、第４図は第１図〜第３図の半
導体装置の等価回路図、第５図及び第６図は従来
における半導体装置の構成例を示した図である。
１……基板、２，１１，１２……酸化膜、３…
…ソース領域、１０，１３，１４，１６……ドレ
イン領域、６……ドリフトチヤネル領域。
1 to 3 are configuration diagrams of an embodiment of the semiconductor device according to the present invention, FIG. 4 is an equivalent circuit diagram of the semiconductor device of FIGS. 1 to 3, and FIGS. 5 and 6 are conventional diagrams. FIG. 2 is a diagram showing a configuration example of a semiconductor device in FIG. 1... Substrate, 2, 11, 12... Oxide film, 3...
... Source region, 10, 13, 14, 16... Drain region, 6... Drift channel region.
Claims (1)
純物濃度のドレイン領域を形成し、この領域を中
心にして周辺に、レーストラツク形状に、内側か
ら、低不純物濃度のドリフトチヤネル領域、ゲー
ト領域及びソース領域を形成してＭＯＳ ＦＥＴ
を構成した半導体装置において、 前記ドレイン領域の半円弧部であつて前記ドレ
イン領域とドリフトチヤネル領域の接合面の近傍
を除く部分の上に形成されていて他の部分の酸化
膜よりも厚い酸化膜と、 前記ドレイン領域とドリフトチヤネル領域の接
合面の近傍で前記厚い酸化膜と重ならない部分に
形成された幅の狭い高不純物濃度のドレイン領域
、を具備したことを特徴とする半導体装置。[Claims for Utility Model Registration] A drain region with a high impurity concentration is formed in the shape of two semicircular arc parts connected by a straight part, and a drain region with a low impurity concentration is formed around this region in a racetrack shape from the inside. MOS FET by forming a concentration drift channel region, gate region and source region
In the semiconductor device comprising: an oxide film formed on a semicircular arc portion of the drain region excluding the vicinity of the junction surface between the drain region and the drift channel region, the oxide film being thicker than the oxide film in other parts; and a narrow drain region with a high impurity concentration formed in a portion that does not overlap with the thick oxide film near a junction surface between the drain region and the drift channel region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9670787U JPS642455U (en) | 1987-06-24 | 1987-06-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9670787U JPS642455U (en) | 1987-06-24 | 1987-06-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS642455U true JPS642455U (en) | 1989-01-09 |
Family
ID=31321781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9670787U Pending JPS642455U (en) | 1987-06-24 | 1987-06-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS642455U (en) |
-
1987
- 1987-06-24 JP JP9670787U patent/JPS642455U/ja active Pending
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