JPS6425433A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6425433A
JPS6425433A JP62181463A JP18146387A JPS6425433A JP S6425433 A JPS6425433 A JP S6425433A JP 62181463 A JP62181463 A JP 62181463A JP 18146387 A JP18146387 A JP 18146387A JP S6425433 A JPS6425433 A JP S6425433A
Authority
JP
Japan
Prior art keywords
film
insulating film
sio2
bias sputter
cavity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62181463A
Other languages
Japanese (ja)
Inventor
Takashi Osone
Masanori Fukumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62181463A priority Critical patent/JPS6425433A/en
Publication of JPS6425433A publication Critical patent/JPS6425433A/en
Pending legal-status Critical Current

Links

Landscapes

  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)

Abstract

PURPOSE:To bury an insulating film in a flat structure having no cavity by correcting the film in a groove so as to have a smooth slope by a bias sputter depositing method. CONSTITUTION:After grooves are formed on a semiconductor substrate 1, a CVD SiO2 film is formed as a first insulating film 10 on a whole surface. Then, an SiO2 film of a second insulating film 11 is formed by a bias sputter depositing method. A CVD SiO2 film is formed as a third insulating film 13 on the upper surface. In this case, since the surface of the base 11 is made of the bias sputter deposited SiO2 film, it has a smooth slope, and the film 12 can be formed without cavity. Then, a first photoresist film 4 and a second photoresist film 5 are formed, and etched back to obtain a shape shown in Figure (d).
JP62181463A 1987-07-21 1987-07-21 Manufacture of semiconductor device Pending JPS6425433A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62181463A JPS6425433A (en) 1987-07-21 1987-07-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62181463A JPS6425433A (en) 1987-07-21 1987-07-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6425433A true JPS6425433A (en) 1989-01-27

Family

ID=16101196

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62181463A Pending JPS6425433A (en) 1987-07-21 1987-07-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6425433A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5102815A (en) * 1990-12-19 1992-04-07 Intel Corporation Method of fabricating a composite inverse T-gate metal oxide semiconductor device
US5175122A (en) * 1991-06-28 1992-12-29 Digital Equipment Corporation Planarization process for trench isolation in integrated circuit manufacture
US5459096A (en) * 1994-07-05 1995-10-17 Motorola Inc. Process for fabricating a semiconductor device using dual planarization layers
KR20010058498A (en) * 1999-12-30 2001-07-06 박종섭 Method of forming trench type isolation layer in semiconductor device
KR100298873B1 (en) * 1997-10-29 2001-11-30 김영환 Flattening method of semiconductor device
US6599811B1 (en) 1998-02-12 2003-07-29 Nec Corporation Semiconductor device having a shallow isolation trench
KR100476372B1 (en) * 1997-12-30 2005-07-07 주식회사 하이닉스반도체 Trench type isolation layer formation method for semiconductor devices with different trench widths

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5102815A (en) * 1990-12-19 1992-04-07 Intel Corporation Method of fabricating a composite inverse T-gate metal oxide semiconductor device
US5175122A (en) * 1991-06-28 1992-12-29 Digital Equipment Corporation Planarization process for trench isolation in integrated circuit manufacture
US5459096A (en) * 1994-07-05 1995-10-17 Motorola Inc. Process for fabricating a semiconductor device using dual planarization layers
KR100298873B1 (en) * 1997-10-29 2001-11-30 김영환 Flattening method of semiconductor device
KR100476372B1 (en) * 1997-12-30 2005-07-07 주식회사 하이닉스반도체 Trench type isolation layer formation method for semiconductor devices with different trench widths
US6599811B1 (en) 1998-02-12 2003-07-29 Nec Corporation Semiconductor device having a shallow isolation trench
KR20010058498A (en) * 1999-12-30 2001-07-06 박종섭 Method of forming trench type isolation layer in semiconductor device

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