JPS6425625A - Multistage logic circuit - Google Patents

Multistage logic circuit

Info

Publication number
JPS6425625A
JPS6425625A JP62181059A JP18105987A JPS6425625A JP S6425625 A JPS6425625 A JP S6425625A JP 62181059 A JP62181059 A JP 62181059A JP 18105987 A JP18105987 A JP 18105987A JP S6425625 A JPS6425625 A JP S6425625A
Authority
JP
Japan
Prior art keywords
logic
positive
output
dynamic
negative logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62181059A
Other languages
Japanese (ja)
Inventor
Masahiro Iwamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62181059A priority Critical patent/JPS6425625A/en
Publication of JPS6425625A publication Critical patent/JPS6425625A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals
    • H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To directly connect optimum input and output in response to the load driving capability of the circuit and the extent of load by providing N, PMOS dynamic circuits of positive/negative logic, N, PMOS bipolar composite dynamic circuits of positive/negative logic. CONSTITUTION:The positive logic NMOS dynamic circuit and/or NMOS bipolar composite dynamic circuits 110, 130 receive the positive logic input signal and output the negative logic signal. On the other band, the negative logic PMOS dynamic circuit and/or PMOS bipolar dynamic circuit 120 receive the negative logic input signal and output the positive logic signal. Thus, the output of the positive logic dynamic circuit 110 and the input of the negative logic dynamic circuit 120, and the output of the negative logic dynamic circuit 120 and the input of the positive logic dynamic circuit 130 are connected directly without adding a polarity inverting means.
JP62181059A 1987-07-22 1987-07-22 Multistage logic circuit Pending JPS6425625A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62181059A JPS6425625A (en) 1987-07-22 1987-07-22 Multistage logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62181059A JPS6425625A (en) 1987-07-22 1987-07-22 Multistage logic circuit

Publications (1)

Publication Number Publication Date
JPS6425625A true JPS6425625A (en) 1989-01-27

Family

ID=16094062

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62181059A Pending JPS6425625A (en) 1987-07-22 1987-07-22 Multistage logic circuit

Country Status (1)

Country Link
JP (1) JPS6425625A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58191530A (en) * 1982-05-04 1983-11-08 Toshiba Corp Logical circuit
JPS6020634A (en) * 1983-07-15 1985-02-01 Nec Corp Cmos logical circuit
JPS60235526A (en) * 1984-05-08 1985-11-22 Mitsubishi Electric Corp Cmos dynamic logical circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58191530A (en) * 1982-05-04 1983-11-08 Toshiba Corp Logical circuit
JPS6020634A (en) * 1983-07-15 1985-02-01 Nec Corp Cmos logical circuit
JPS60235526A (en) * 1984-05-08 1985-11-22 Mitsubishi Electric Corp Cmos dynamic logical circuit

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