JPS642954B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides an edge signal for edging the periphery of characters displayed on a screen by a character generator used in ITV (Industrial Television) systems, etc., in order to make the characters easier to see. This invention relates to an edge generation circuit that generates an edge.

Conventionally, there has been a circuit of this type as shown in FIG. In the figure, 1 is a delay line that delays the input character signal S1 for a certain period of time T1, and 2 is an Ex-OR gate that takes the exclusive OR of the signal S2 delayed by the delay line 1 and the character signal S1 before the delay. , the delay line 1 and the Ex-OR gate 2 form an edge signal S3 in the horizontal direction of the screen. Also, 3
is a second delay line that delays the input character signal S1 by a time T2 corresponding to one horizontal line of the screen, and 4 is the exclusive OR of the delayed signal S4 by the second delay line 3 and the character signal S1 before the delay. In the second Ex-OR gate,
These delay line 3 and Ex-OR4 form an edge signal S5 in the vertical direction of the screen. Reference numeral 5 denotes a logical sum (OR) gate, which mixes the above-mentioned horizontal and vertical edge signals S3 and S5 and outputs the mixture as an edge signal S6.

That is, to explain in detail using Figures 2 and 3, the character signal S1 is delayed by a certain period of time T1 by the delay line 1 as shown in Figure 2b, and is input to the Ex-OR gate 2, The exclusive OR with the character signal S1 shown in FIG.
S1 is input to the second delay line 3 and delayed by a time T2 corresponding to one horizontal line of the screen as shown in FIG. The exclusive OR is taken and a vertical edge signal S5 as shown in FIG. 3c is output. Then, these horizontal and vertical edge signals S3 and S5 are mixed at an OR gate 5 to obtain an edge signal for edging the periphery of the displayed character.

Note that FIG. 2 d and FIG. 3 d each represent a composite signal of characters and edges, and FIG. 2 d relates to the horizontal direction, and FIG. 3 d relates to the vertical direction. The shaded area inside represents the edge signal portion.

However, since the conventional edge generation circuit is configured as described above, expensive components such as the delay line 1 and the second delay line 3 must be used, and as a result, the entire circuit is The drawback was that it was expensive. Also, Figure 2 a and d or Figure 3
As is clear from a comparison of Figures a and d, there was a drawback in that the display width of the character signal S1 was partially omitted due to the edge signal and became smaller, which affected the character shape.

The present invention has been developed in view of the above points, and it is possible to simultaneously digitally process the latest three lines of pixel line signals of characters without using expensive parts, and without affecting the pixel line signals of characters. An object of the present invention is to provide an edge generation circuit that can easily obtain edge signals.

In order to achieve this purpose, there is provided a memory device that stores the latest two lines of pixel line signals of characters, and a memory update circuit that inputs the pixel line signal of the next line and updates the stored contents of the memory device.
A determination circuit that receives pixel line signals for a total of three lines from the storage device and the storage update device and generates a pixel state signal representing any one of "edge", "character", or "empty", and operation timing; and a timing circuit that generates a signal.
The memory update circuit inputs the pixel line signal of the next line and sends it to the discrimination circuit, and the storage device synchronizes with it and sends the stored pixel line signal for the latest two lines to the discrimination circuit. ,
The pixel line signal of the next line is input from the memory update circuit to update the memory contents, and the discriminating circuit shifts the pixel line signal for three lines related to these inputs and uses the three bits of each one bit shift to perform the three pixel line signals.
The character pixel states in a ×3 matrix are sequentially extracted and determined, and if matrix elements 2 and 2 are character writing pixels, a pixel state signal representing "character" is determined.
If there is a character display pixel in one or more of the matrix elements other than matrix elements 2 and 2, and matrix elements 2 and 2 are not text display pixels, the pixel state signal representing "edge" is sent to the other matrix state. In this case, a pixel state signal representing "empty" is sent out as a pixel state signal of the matrix elements 2, 2 each time the matrix is taken out.

An embodiment of the present invention according to FIG. 4 is shown. In the figure, 6 is a storage device that stores two lines of character horizontal pixel line signals made up of parallel 8 bits, 7 is a memory update circuit that updates the storage contents of the storage device 6, and 8 is a data bus, as described above. The memory update circuit 7 includes a selector 71 that receives a parallel 8-bit character horizontal pixel line signal, divides it into two, and converts it into a parallel 4-bit signal, and a parallel 4-bit signal from the selector 71 and a data bus 8. It consists of a parallel 8-bit register that temporarily stores parallel 4-bit signals stored in the storage device 6 that are inputted via the register. Reference numeral 9 denotes a discrimination circuit that receives horizontal pixel line signals for the latest three lines from the storage device 6 and memory update circuit 7 and discriminates and determines the display form of each pixel. Shift registers 91 to 93 that convert the data into serial data, a gate 94 that processes the output data of the shift registers 91 to 93 and outputs an edge signal or a character signal, and a gate 94 that processes the output data of the shift registers 91 to 93 and outputs an edge signal or a character signal; Flip-flops 95 and 96 are provided for synchronization. 10 is a timing circuit, and a storage device 6
In response to the clock pulse, a read/write timing signal for the storage device 6 and a timing signal for outputting the data in the register 72 onto the data bus 8 are generated.

Next, the operation of the illustrated embodiment having such a configuration will be explained using FIGS. 5a to 5d.

Now, suppose that a parallel 8-bit character pixel line signal related to the i-th row shown in FIG. , the parallel 4-bit signal related to the division is directly sent to the shift register 93 and also supplied to the register 72 for updating the contents of the storage device 6. At this point, the storage device 6 has pixel line signals related to the i-2th row and i-1th row shown in FIG. The line signal is output onto the data bus 8, and the upper 4 bits of the previous line on the data bus 8 are stored in the register 72.
This means that the 4-bit signal output from the selector 71 and the 4-bit signal from the previous line from the storage device 6 are stored. Next, the register 72 outputs these 8-bit signals onto the data bus 8, and the data is stored in the storage device 6. This operation is repeated, and as a result, the latest two lines are stored in the storage device 6. i.e., the i-th pixel line signal shown in FIG.
Pixel line signals related to the 1st and i-th rows are stored.

In addition, in parallel with this memory update operation, pixel line signals for two lines related to the i-2th row and the i-1th row output from the storage device 6 onto the data bus 8 are sent to the shift register 91 and shifted. register 92
are input respectively. In other words, in addition to the input from the selector 71 to the shift register 93, the pixel line signals for the latest three lines are given to the shift registers 91-93. Next, the data stored in the shift registers 91 to 93 are simultaneously shifted one bit at a time and inputted to the gate 94, and the gate 94 uses three bits of each of the shifted line data, as shown in FIG. 5b. Detect a 3×3 matrix such as
Determines the display form of pixels and detects edge signals and the like.

That is, matrix elements 2 and 2 are in the area shown in FIG. 5c.
In the first case, where the pixel is a character display pixel like RA, the flip-flop 95 is made to send out a display character signal, while the flip-flop 96 is made to stop sending out an edge signal, so that the pixels related to matrix elements 2 and 2 are text display pixels. Outputs that it is a pixel. In the second case where at least some of the elements other than matrix elements 2 and 2 have character display pixels as in the area RB of FIG. 5c, the flip-flop 9
The transmission of the display character signal No. 5 is stopped, and on the other hand, the edge signal is sent from the flip-flop 96 to output that the pixels of matrix elements 2 and 2 are pixels that should become edges. Furthermore, in the third case where there is no character marking pixel in any element of the 3x3 matrix, such as the area RC shown in FIG. First, it outputs that the pixels associated with matrix elements 2 and 2 are neither character writing pixels nor pixels that should become edges.

Extraction of such a 3×3 matrix, and
The operation of determining and judging the display form of the pixels is performed sequentially for each 1-bit shift of the shift registers 91 to 93, and as a result, the edge is determined for the pixel marked with a circle in FIG. 5d for the character signal shown in FIG. 5a. A signal can be output.

Note that timing signals for transmitting and receiving signals between the storage device 6 and the data bus 8, sending signals from the register 72 to the data bus 8, writing signals to the shift registers 91 to 93, etc. Circuit 10 is created based on address signals and clock pulses. Further, the signal sent to the storage device 6 in FIG. 4 is an address signal indicating the address of a display screen (not shown).

In the above explanation of the illustrated embodiment, an edge signal etc. is created by focusing on a horizontal pixel line signal, but an edge signal is created by focusing on a vertical pixel line signal. Of course, it is good to do so. Also, although the above explanation was given for 8 bits per line,
Of course, the present invention is not limited to this number of bits.

As described above, according to the present invention, the edge generation circuit is constructed using only digital circuits without using expensive parts such as delay lines, so that it has the effect of high accuracy and low cost of the entire circuit, and also Since the edge display pixels do not interfere with the character pixels, this has the effect of making the displayed characters easier to see.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional edge generation circuit, FIGS. 2 and 3 are explanatory diagrams showing the operation timing of the circuit in FIG. 1 in the horizontal or vertical direction and the process of edge signal generation, respectively. The figure is a block diagram showing an edge generation circuit according to an embodiment of the present invention, and FIGS. 5a to 5d are auxiliary explanatory diagrams to assist in explaining the operation of the circuit of the embodiment shown in FIG. 6...Storage device, 7...Memory update circuit, 8...
Data bus, 9...discrimination circuit, 10...timing circuit, 71...selector, 72...register,
91-93...Shift register, 94...Gate, 95, 96...Flip-flop. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A memory device that stores pixel line signals of characters for the latest two lines, a memory update circuit that inputs pixel line signals of the next line and updates the memory contents of the memory device, and a A discrimination circuit receives pixel line signals for a total of three lines and generates a pixel state signal representing "edge", "character", or "empty", and a timing circuit generates an operation timing signal. The storage update circuit inputs the pixel line signal of the next line and sends it to the discrimination circuit, and the storage device synchronizes with it and sends the stored pixel line signals for the latest two lines to the discrimination circuit. At the same time, the pixel line signals of the next line are input from the memory update circuit to update the memory contents, and the above-mentioned discrimination circuit shifts the pixel line signals for three lines related to these inputs, and calculates the 3 bits for every 1 bit shift. is used to sequentially extract and discriminate the character pixel states in a 3x3 matrix, and when matrix elements 2 and 2 are character writing pixels, the pixel state signal representing "character" is determined from the pixel state signals other than matrix elements 2 and 2. If one or more of the matrix elements has a character display pixel, and matrix elements 2 and 2 are not character display pixels, a pixel state signal indicating "edge" is output, and in the case of other matrix states, a pixel state signal indicating "empty" is output. An edge generation circuit configured to send out a pixel state signal as a pixel state signal of the matrix elements 2, 2 each time a matrix is taken out.