JPS642973B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a multiple reciprocating circuit that takes advantage of the repeatability that accompanies high integration of logic circuits.

Conventionally, using a parity check circuit to check the operation of complex arithmetic circuits such as multiplication circuits and division circuits requires a large-scale circuit configuration, so a method using a recipe check has been known. .

Regarding the principle of residue checks,
For example, "ERROR DETECTION LOGIC FOR
DIGITAL COMPUTERS”FREDERICK F
SELLERS JR, MU−YUE HS IAO, LEROY
Written by W BEARNSON, McGRAW HILL BOOK
Since it is disclosed in COMP ANY, published in 1968, it will not be explained here, but the main points of recipe check, using multiplication as an example, are as follows. In other words, the value obtained by calculating the residue (remainder after dividing by 3) for each of the multiplicand and the multiplier, and multiplying the obtained residue by the multiplier, is the same as the residue calculated from the value obtained by multiplying the multiplicand and the multiplier by the multiplier. Based on this principle, the two recipes are compared to check the operation of the multiplier.

Therefore, in general, there is provided a means for generating a recipe for input data to an arithmetic unit and obtaining an operation result for the generated recipe; a means for generating a recipe for the operation result for the input data;
A means for comparing the recipes obtained by the two methods is required.

When the above input data is divided into ²ⁿ parts (where n is a positive integer) and operated, ²ⁿ partial operation results are obtained, so a recipe is generated for each partial operation result, In order to obtain the final recipe using the result, an n-stage [2 ⁿ (where n=1, 2, 3, . . . , n)] recipe calculation circuit is required.

On the other hand, with the recent increase in the degree of integration of logic devices, importance has been placed on repeatability when circuits of the logic device are divided.

This repeatability can be achieved by, for example, adding a specific circuit to the divided logic circuit when the logic device is divided into integrated circuit units.
Even if the additional circuit is not used in a logic block with a logic device, it can be shared by multiple logic blocks, and as a result, the types of integrated circuits can be reduced, the amount used can be increased, and the integrated circuit can be made more economical. It is based on this principle, and commonization of circuits is an essential condition.

Therefore, when considering the recipe check circuit from the viewpoint of repeatability, especially when input data is divided into ^{2n pieces} for calculation, there is a circuit that performs the final calculation on the recipe generation result of the calculation result, and a circuit that performs the final calculation on the recipe generation result of the calculation result, and a circuit that performs the final calculation on the recipe generation result of the calculation result. The circuit that generates and checks the calculated results is a common circuit for the 2 ⁿ divided calculation circuits, which becomes a factor that hinders the repeatability described above.

Under these circumstances, a method of configuring a reciprocating circuit that is suitable for a 2n ^- divided arithmetic circuit and improves repeatability has been awaited.

[Conventional technology]

Figure 2 shows an example of a case where a recipe check is performed on an adder circuit that is divided into two (2 ⁿ divisions correspond to n = 1), where 1 is input data register A, 2 is input data register B, Each is divided into two parts, and the lower parts are respectively Aa and
Ba, the upper part is shown as Ab, Bb. 31 and 32 are partial adders (+), 41 and 42 are recipe generation circuits (RES GEN) for the partial addition results, and 5 is a recipe addition for final addition of the residues generated by the recipe generation circuits (RES GEN) 41 and 42. circuit (RES ADD), 6 is a comparison circuit (COMP), 71,
72 is a recipe generation circuit (RES GEN) for input data, and 8 is a recipe adder (RES GEN).
ADD), the final recipe of the input data IN RES
Output. And 9 is a final output register.

Now, when input data is set in the input data register A1 and the input data register B2, the lower parts Aa and Ba of the data are sent to the partial adder (+) 31.
, and sends the carry (C) to the partial adder (+) 32 and outputs the lower partial sum SA. At the same time, the upper portions Ab and Bb of the data are partially added together with the carry (C) by a partial adder (+) 32, and an upper partial sum SB is output.
Then, by inserting the partial sums SA and SB into the respective division positions of the final output register 9, the final addition result can be obtained.

The above partial sum SA is calculated by the recipe generation circuit (RES).
The partial sum SB is input to the residue generation circuit (RES GEN) 42 to generate a residue for the upper partial addition result, and the partial sum SB is input to the residue generation circuit (RES GEN) 42 to generate a residue for the upper partial addition result. The result is input to a recipe adder circuit (RES ADD) 5 to obtain the final recipe.

On the other hand, the recipe for input data [BES(A),
RES(B)] is generated by a recipe generation circuit (RES GEN) 71,
72 and added by a recipe addition circuit (RES ADD) 8, and the final recipe IN RES [RES (A+B)] for the input data is output as the expected value for the addition.

Final receipt IN RES for this input data
The comparison circuit (COMP) 6 compares the addition result of the recipe with respect to the above-mentioned two-division addition result, and if they do not match, the partial adder (+) 31 or 3
2, it operates to output an error signal ERR.

This example is a recipe check circuit that divides input data into two and performs calculations; however, it includes a recipe generation circuit (RES GEN) 5 that is independent of the two divided calculation circuits #1 and #2, and a comparison circuit ( COMP)
It is distinctive in that it has a number 6.

[Problem that the invention seeks to solve]

As is clear from FIG. 2, in the conventional two-division calculation method, for example, two adder circuits #1 and #2
can be realized with the same logic configuration, achieving so-called repeatability, but in order to obtain the final recipe of the addition result, a recipe addition circuit (RES ADD) is required.
5 and comparator circuit (COMP) 6, which are separate circuit blocks from the above adder circuit, are required.
When attempting to achieve high integration, the number of types of integrated circuits increases, which poses the problem of impairing repeatability due to high integration.

In view of the above-mentioned drawbacks of the conventional art, the present invention includes a recipe calculation circuit that is required to obtain the final recipe for the calculation result in the divided calculation circuits, and performs the recipe check individually in each calculation circuit, thereby achieving repeatability. The purpose is to provide a method to improve the quality of the product.

[Means for solving problems]

The purpose of this is to divide the input data into 2 ⁿ (n is an integer greater than 1), perform partial operations using 2 ⁿ arithmetic circuits, and insert the output of each arithmetic circuit into the corresponding division position. This is achieved by the recipe check circuit of the present invention, which includes a recipe exchange circuit required up to the final recipe in each divided arithmetic circuit in a recipe check system of a ^2n- divided arithmetic circuit that obtains a final arithmetic result.

[Effect]

That is, according to the present invention, in a method in which input data is divided into 2 ⁿ (n is an integer greater than 1) and partial operations are performed using 2 ⁿ arithmetic circuits, when performing a recipe check for the operation, the divided data is Since each divided circuit includes a recipe exchange circuit required up to the final recipe, it is possible to individually check the recipe by ²ⁿ multiplexing in each divided circuit, and the repeatability due to ²ⁿ division is improved. [Example] Examples of the present invention will be described in detail with reference to the drawings.
Figure 1A is a block diagram of an example of an adder circuit that is divided into two (2 ⁿ divisions and n = 1), and B is a block diagram of an example of an adder circuit that is divided into 4 divisions (2 ⁿ divisions and n = 2). FIG. 2 is a diagram schematically showing an example of a recipe exchange circuit in an arithmetic circuit (corresponding to the above).

In Fig. 1A, the same reference numerals as in Fig. 2 indicate the same functional blocks, and 51 and 52 are the same as the recipe adder circuit (RES ADD) 5 in Fig. 2. The difference is that the residue to be added to the residue of the dividing circuit is taken in. Further, 61 and 62 are the same as the comparator circuit (COMP) 6 in FIG. 2, and are distinctive in that they are provided in the respective divided adder circuits #1 and #2.

Regarding addition processing when implementing the present invention,
Since this is exactly the same as the conventional system explained in FIG. 2, the explanation will be limited to the reciprocating circuit which is the main focus of the present invention.

In the present invention, the residues for the partial addition results in the respective two-divided adder circuits #1 and #2 are stored in a recipe generation circuit (RES GEN) 4.
1 and 42, and send the results to the other adder circuits #2 and #1 (that is, exchange them), and the respective recipe adder circuits (RES ADD) 51,
52, there is a point where the final addition of the recipe is performed.

That is, in the conventional method, the partial addition result SA,
The residue generation circuit (RES) generates the residue for SB.
GEN) 41, 42 and the final addition is performed in the recipe adder circuit (RES ADD) 5. However, in the present invention, 2 ⁿ multiplexing is performed in each adder circuit #1, #2. (In this embodiment, two-multiplex) final addition of the residues is performed.

Then, the result of the final addition of the residues is added to the output value of the residue addition circuit (RES ADD) 8, which is the final residue for the input data (that is, the expected value of the final residue for the main addition), and the output value of the residue addition circuit (RES ADD) 8, and the respective addition circuits #1 and #. Comparing circuits (COMP) 61 and 62 provided in the second section perform two multiple comparisons.

Therefore, if the comparison circuit (COMP) 61, 6
2, if a mismatch is output, the combination of the mismatch signals ERR#1 and #2 will result in
The following failure analysis is possible. That is, if ERR#1, ERRR#2 = 0, 0: No failure location.

When ERR#1, ERR#2 = 1, 0: Failure of the recipe addition circuit (RES ADD) 51 or comparison circuit (CCMP) 61.

When ERR#1, ERR#2 = 0, 1: Failure of the recipe addition circuit (RES ADD) 52 or comparison circuit (CMP) 62.

When ERR#1, FRR#2 = 1, 1: There is a failure in the partial adder (+) 31 or 32, or both, or the recipe generation circuit (RES
GEN) 41 or 42, or both disorders;
Or recipe addition circuit (RES ADD) 51,
52 disabilities.

That is, in the present invention, the recipe addition circuits (RES ADD) 51 and 52, which could not be distinguished in the conventional method,
[Conventional rate adder circuit (RES ADD)]
5 compatible] or comparison circuit (COMP) 61, 62
It becomes possible to determine the failure of the conventional comparison circuit (compatible with COM6).

Next, in FIG. 1B, an example of four divisions will be explained.

In this case as well, the addition process is performed in the same way as in the two-division case, so the explanation will be limited to the reception check circuit.

In this figure, 41 to 44 correspond to recipe generation circuits (RES GEN) 41 and 42 in figure A, and 51 to 54 correspond to recipe addition circuits (RES ADD) 51 and 52 in figure A. In the case of this four-part division, recipe adder circuits (RES ADD) indicated by 51' to 54' are required. The comparison circuits (COMP) 61 to 64 are the same as the comparison circuits (COMP) 61 and 62 in Fig.
It is simply 4 times multiplexed.

That is, if input data (not shown) is divided into four parts and each part is a, b, c, and d, then Aa, Ab, Ac, Ad, and Ba, Bb correspond to the two input data A and B. , Bc, and Bd become input data to this four-division adder circuit. Then, the residue generation circuit (RES) generates the residue for Aa+Ba.
GEN) 41 and outputs the recipe. In the same way, create recipe b, c, d respectively.
is generated.

Regarding the recipes a to d for the above partial addition results, the recipe addition circuit (RES ADD51 to 54)
, the partial addition of the recipe a+b, or c+
d is executed in two multiplexes. At this time, it is necessary to replace the recipes a, b or c, d.

Then, the addition a+b+c+d for obtaining the final recipe for the operation result is added to the recipe addition circuit (RES ADD) 5 in each divided addition circuit.
1' to 54' are executed in four multiplexes. In this case, it is necessary to exchange the partial addition values a+b or c+d of the recipe.

The final recipe a+b+c added in the four multiplexes
+d is the expected value IN RES of the recipe for the main addition result obtained from the input data A and B in the comparison circuits (COMP) 61 to 64 provided in each of the divided adder circuits, and the 4-multiplex are compared.

As is clear from the above explanation, in the 4-division addition circuit, the recipes a to d for the partial addition results are
, where a + b or c + d is performed, the exchange of recipes a, b or recipes c, d is performed, and where a + b + c + d is performed, the exchange of the partial addition value a + b or c + d of the recipe is performed. Ru.

Generally, when performing a recipe check in a system in which input data is divided into 2 ⁿ (where n is an integer greater than 1) and calculations are performed, it is necessary to exchange the partial addition results of n recipes.

In this example, an operation (here, addition) method in which input data is divided into two, four, generally 2 ⁿ (where n is an integer greater than 1) and the operation is performed will be explained as an example. However, in view of the gist of the present invention, it goes without saying that it is not limited to the above-mentioned exponential division, but can also be applied to an arithmetic method that performs an operation as n-division (where n is an integer greater than 1). It is.

〔Effect of the invention〕

As described above in detail, the residu check circuit of the present invention divides input data into 2 ⁿ (n is an integer greater than 1) and performs partial operations using 2 ⁿ arithmetic circuits. In order to perform the recipe check, each divided circuit includes a recipe exchange circuit required up to the final recipe. Therefore, each divided circuit can perform the recipe check individually by ²ⁿ multiplexing, and This has the effect of improving repeatability due to ²ⁿ division.

[Brief explanation of drawings]

Figure 1 is a block diagram of an embodiment of the present invention for an adder circuit divided into two parts, and a diagram schematically showing a recipe check circuit in an adder circuit divided into four parts. , is a diagram showing an example of a case where a recipe check is performed using a conventional method. In the drawing, 1 indicates input data register A, 2
is input data register B, 31 and 32 are partial adders (+), and 41 to 44 are recipe generation circuits (RES).
GEN), 5, 51 to 54 are recipe addition circuits (RES ADD), 51' to 54' are recipe addition circuits (RES ADD), 6, 61 to 64 are comparison circuits (COMP), and 71 and 72 are recipe generation circuits. (RES GEN), 8 is the recipe addition circuit (RES
ADD), 9 is the final output register, Aa~Ad, Ba~
Bd is divided input data, SA, SB are partial addition sums, a, b, c, d are recipe generation values, IN
RES is the final recipe for input data, ERR,
ERR#1 to ERR#4 indicate recipe check error signals, respectively.

Claims (1)

[Claims] 1. Divide input data into 2 ⁿ (n is an integer greater than 1), perform partial calculations using 2 ⁿ arithmetic circuits, and insert the output of each arithmetic circuit into the corresponding division position. According to a recipe check method of a ^2n- divided arithmetic circuit for obtaining a final arithmetic result, each of the divided arithmetic circuits includes a recipe exchange circuit required up to the final recipe. 2 In the above recipe exchange circuit, the nth stage (n
2. The recipe check circuit according to claim 1, wherein the recipe exchange circuit is configured to exchange 2 ⁿ recipe partial operation results.