JPS6430535U - - Google Patents

Info

Publication number
JPS6430535U
JPS6430535U JP1987124922U JP12492287U JPS6430535U JP S6430535 U JPS6430535 U JP S6430535U JP 1987124922 U JP1987124922 U JP 1987124922U JP 12492287 U JP12492287 U JP 12492287U JP S6430535 U JPS6430535 U JP S6430535U
Authority
JP
Japan
Prior art keywords
semiconductor chip
flux
display substrate
black
face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987124922U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987124922U priority Critical patent/JPS6430535U/ja
Publication of JPS6430535U publication Critical patent/JPS6430535U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Liquid Crystal (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の実施例を示す断面図、第２図
及び第３図は従来例を示す図である。 １は表示用基板、２は半導体チツプ、３は導線
、４は黒色フラツクス、５はバンプ電極。 FIG. 1 is a sectional view showing an embodiment of the present invention, and FIGS. 2 and 3 are views showing a conventional example. 1 is a display substrate, 2 is a semiconductor chip, 3 is a conductive wire, 4 is a black flux, and 5 is a bump electrode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 表示用透明基板上に半導体チツプがフエイスダ
ウンボンデイングされる表示用基板において、前
記半導体チツプ表面に半田接合を可能とするため
に付着されるフラツクスを黒色フラツクスとし、
前記透明基板上に設けられた複数の接続電極上に
前記半導体チツプをフエイスダウンボンデイング
した際、前記半導体チツプと対向する前記透明基
板上に前記黒色フラツクスが付着され、前記黒色
フラツクスが遮光膜となることを特徴とする表示
用基板。 In a display substrate on which a semiconductor chip is face-down bonded onto a transparent display substrate, the flux attached to the surface of the semiconductor chip to enable solder bonding is black flux,
When the semiconductor chip is face-down bonded onto the plurality of connection electrodes provided on the transparent substrate, the black flux is deposited on the transparent substrate facing the semiconductor chip, and the black flux becomes a light-shielding film. A display substrate characterized by:
JP1987124922U 1987-08-17 1987-08-17 Pending JPS6430535U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987124922U JPS6430535U (en) 1987-08-17 1987-08-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987124922U JPS6430535U (en) 1987-08-17 1987-08-17

Publications (1)

Publication Number Publication Date
JPS6430535U true JPS6430535U (en) 1989-02-23

Family

ID=31375069

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987124922U Pending JPS6430535U (en) 1987-08-17 1987-08-17

Country Status (1)

Country Link
JP (1) JPS6430535U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999032304A1 (en) * 1997-12-22 1999-07-01 Hitachi, Ltd. Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999032304A1 (en) * 1997-12-22 1999-07-01 Hitachi, Ltd. Semiconductor device

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