JPS6431252A - Data bus width transformer - Google Patents

Data bus width transformer

Info

Publication number
JPS6431252A
JPS6431252A JP18911287A JP18911287A JPS6431252A JP S6431252 A JPS6431252 A JP S6431252A JP 18911287 A JP18911287 A JP 18911287A JP 18911287 A JP18911287 A JP 18911287A JP S6431252 A JPS6431252 A JP S6431252A
Authority
JP
Japan
Prior art keywords
bus
signal
data buffer
bus width
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18911287A
Other languages
Japanese (ja)
Inventor
Isamu Nakayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18911287A priority Critical patent/JPS6431252A/en
Publication of JPS6431252A publication Critical patent/JPS6431252A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To freely use an existing system by CPUs different in a bus width by receiving a data latch timing signal outputted from a control part, a data buffer enable signal and a data buffer input and output direction signal to interface the internal bus and the external bus of the CPU. CONSTITUTION:The control part 119 receives the external access request command BxE, the address signal IAS and the bus width status signal BCY of the CPU 101 to form a single or plural bus cycle timing signals OR/W corresponding to the bus width of the external bus and a single or plural address signals OASs corresponding to the bus width of the external bus. A data buffer/ latch part receives the data latch timing signal DRTM 124 outputted from the control part 119, the data buffer enable signal DBEM 125 and the data buffer input and output direction signal DBIOM 126 to interface the internal bus and the external bus of the CPU 101. Thereby, the CPUs different in the bus width can freely use the existing system.
JP18911287A 1987-07-28 1987-07-28 Data bus width transformer Pending JPS6431252A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18911287A JPS6431252A (en) 1987-07-28 1987-07-28 Data bus width transformer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18911287A JPS6431252A (en) 1987-07-28 1987-07-28 Data bus width transformer

Publications (1)

Publication Number Publication Date
JPS6431252A true JPS6431252A (en) 1989-02-01

Family

ID=16235575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18911287A Pending JPS6431252A (en) 1987-07-28 1987-07-28 Data bus width transformer

Country Status (1)

Country Link
JP (1) JPS6431252A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5341481A (en) * 1989-09-11 1994-08-23 Hitachi, Ltd. Method and apparatus for dynamically changing bus size using address register means and comparator means as bus size detectors
US6414609B1 (en) 2001-04-16 2002-07-02 Fujitsu Limited Data width conversion apparatus and data processing apparatus
US6415445B1 (en) 1999-01-18 2002-07-09 Mizuno Corporation Sports glove

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5729935B2 (en) * 1976-12-23 1982-06-25

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5729935B2 (en) * 1976-12-23 1982-06-25

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5341481A (en) * 1989-09-11 1994-08-23 Hitachi, Ltd. Method and apparatus for dynamically changing bus size using address register means and comparator means as bus size detectors
US5493656A (en) * 1989-09-11 1996-02-20 Hitachi, Ltd. Microcomputer with dynamic bus controls
US6415445B1 (en) 1999-01-18 2002-07-09 Mizuno Corporation Sports glove
US6414609B1 (en) 2001-04-16 2002-07-02 Fujitsu Limited Data width conversion apparatus and data processing apparatus

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