JPS6429145A - Packet switch - Google Patents

Packet switch

Info

Publication number
JPS6429145A
JPS6429145A JP18522287A JP18522287A JPS6429145A JP S6429145 A JPS6429145 A JP S6429145A JP 18522287 A JP18522287 A JP 18522287A JP 18522287 A JP18522287 A JP 18522287A JP S6429145 A JPS6429145 A JP S6429145A
Authority
JP
Japan
Prior art keywords
write
control circuit
access enable
request
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18522287A
Other languages
Japanese (ja)
Inventor
Hideki Kataoka
Tatsuro Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP18522287A priority Critical patent/JPS6429145A/en
Publication of JPS6429145A publication Critical patent/JPS6429145A/en
Pending legal-status Critical Current

Links

Landscapes

  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To attain a packet switch applying R/W common arbitration while a multistage switch is constituted efficiently by outputting an access enable signal when both write/read arbiters are selected by a priority arbiter control circuit and other arbiter outputs a signal representing the absence of an access request input or an access enable output. CONSTITUTION:A priority arbiter control circuit 44 is provided and an access enable signal is outputted when both the write/readout arbiters 41, 42 are selected by the priority arbiter control circuit 44 and the other arbiter outputs a signal representing the absence of the access enable output. Thus, when the request is consecutive, since at least a half of the memory cycle is guaranteed to allocate the write or readout with consecutive request, the arbitration of the R/W common is attained efficiently.
JP18522287A 1987-07-24 1987-07-24 Packet switch Pending JPS6429145A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18522287A JPS6429145A (en) 1987-07-24 1987-07-24 Packet switch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18522287A JPS6429145A (en) 1987-07-24 1987-07-24 Packet switch

Publications (1)

Publication Number Publication Date
JPS6429145A true JPS6429145A (en) 1989-01-31

Family

ID=16167013

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18522287A Pending JPS6429145A (en) 1987-07-24 1987-07-24 Packet switch

Country Status (1)

Country Link
JP (1) JPS6429145A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0435336A (en) * 1990-05-28 1992-02-06 Nec Corp cell switch

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0435336A (en) * 1990-05-28 1992-02-06 Nec Corp cell switch

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