JPS6431448U - - Google Patents
Info
- Publication number
- JPS6431448U JPS6431448U JP12653187U JP12653187U JPS6431448U JP S6431448 U JPS6431448 U JP S6431448U JP 12653187 U JP12653187 U JP 12653187U JP 12653187 U JP12653187 U JP 12653187U JP S6431448 U JPS6431448 U JP S6431448U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- address
- cpu
- selection signal
- bit group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Description
第１図〜第３図はこの考案の一実施例を示す図
、第４図〜第６図は従来の例を示す図である。
１はＣＰＵ、２ａ〜２ｎはメモリ、３はアドレ
スデコーダ、４ａ〜４ｎはパワースイツチング回
路、５はアドレス変換回路である。なお、図中、
同一符号は同一又は相当部分を示す。
1 to 3 are views showing an embodiment of this invention, and FIGS. 4 to 6 are views showing a conventional example. 1 is a CPU, 2a to 2n are memories, 3 is an address decoder, 4a to 4n are power switching circuits, and 5 is an address conversion circuit. In addition, in the figure,
The same reference numerals indicate the same or equivalent parts.
Claims (1)
ドレスを制御し、該当するプログラムをリードす
るＣＰＵ、メモリとＣＰＵの間に位置しＣＰＵか
ら出力されたアドレスの上位ビツト群と下位ビツ
ト群の接続を交換するアドレス変換回路、変換後
のアドレスの上位ビツト群をメモリ選択信号に符
号化するアドレスデコーダ、符号化されたメモリ
選択信号によりメモリに電力を供給するパワース
イツチング回路より構成され、プログラム列の実
行ステツプごとに選択するメモリを切換えながら
動作させることを特徴とするメモリ制御回路。 A memory that stores a program, a CPU that controls the address of this memory and reads the corresponding program, and an address that is located between the memory and the CPU and exchanges connections between the upper bit group and the lower bit group of the address output from the CPU. It consists of a conversion circuit, an address decoder that encodes the high-order bits of the converted address into a memory selection signal, and a power switching circuit that supplies power to the memory using the encoded memory selection signal. A memory control circuit that operates while switching memory to be selected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12653187U JPS6431448U (en) | 1987-08-20 | 1987-08-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12653187U JPS6431448U (en) | 1987-08-20 | 1987-08-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6431448U true JPS6431448U (en) | 1989-02-27 |
Family
ID=31378138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12653187U Pending JPS6431448U (en) | 1987-08-20 | 1987-08-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6431448U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0333951A (en) * | 1989-06-29 | 1991-02-14 | Nec Corp | Microcomputer system |
-
1987
- 1987-08-20 JP JP12653187U patent/JPS6431448U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0333951A (en) * | 1989-06-29 | 1991-02-14 | Nec Corp | Microcomputer system |