JPS6431462A - Manufacture of vertical bipolar transistor - Google Patents

Manufacture of vertical bipolar transistor

Info

Publication number
JPS6431462A
JPS6431462A JP62188149A JP18814987A JPS6431462A JP S6431462 A JPS6431462 A JP S6431462A JP 62188149 A JP62188149 A JP 62188149A JP 18814987 A JP18814987 A JP 18814987A JP S6431462 A JPS6431462 A JP S6431462A
Authority
JP
Japan
Prior art keywords
region
type
layer
isolating
diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62188149A
Other languages
Japanese (ja)
Inventor
Tomoyuki Hikita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP62188149A priority Critical patent/JPS6431462A/en
Publication of JPS6431462A publication Critical patent/JPS6431462A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a vertical bipolar transistor in which the width of a base region can be freely altered by etching a predetermined region for separately diffusing in advance before an isolating region is formed. CONSTITUTION:An N<+> type buried layer 2 is formed on a P-type silicon substrate, a P<+> type buried layer 3 to become the collector region of a vertical PNP transistor is formed on the layer 2, and a P<+> type buried layer 4 to become an isolating region is simultaneously formed on a P-type silicon substrate 1. Then, an N-type epitaxial layer 5 is grown on a whole surface, an oxide film 6 which becomes a diffusing mask of an isolating diffusion (P<+>) from above is formed, and an oxide film on the diffused region from above is removed by patterning by means of a predetermined photoetching technique. The mask material (photoresist layer 7) used for patterning is utilized as it is, and an N-type epitaxial layer to become the isolating region is etched in a predetermined amount. This setup suppresses the upward diffusion into the epitaxial layer of the P<+> type buried layer to a small value. After a P<+> type isolating region 8 is formed, a base diffusion and an emitter diffusion are performed.
JP62188149A 1987-07-27 1987-07-27 Manufacture of vertical bipolar transistor Pending JPS6431462A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62188149A JPS6431462A (en) 1987-07-27 1987-07-27 Manufacture of vertical bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62188149A JPS6431462A (en) 1987-07-27 1987-07-27 Manufacture of vertical bipolar transistor

Publications (1)

Publication Number Publication Date
JPS6431462A true JPS6431462A (en) 1989-02-01

Family

ID=16218608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62188149A Pending JPS6431462A (en) 1987-07-27 1987-07-27 Manufacture of vertical bipolar transistor

Country Status (1)

Country Link
JP (1) JPS6431462A (en)

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