JPS6433752U - - Google Patents
Info
- Publication number
- JPS6433752U JPS6433752U JP1987127769U JP12776987U JPS6433752U JP S6433752 U JPS6433752 U JP S6433752U JP 1987127769 U JP1987127769 U JP 1987127769U JP 12776987 U JP12776987 U JP 12776987U JP S6433752 U JPS6433752 U JP S6433752U
- Authority
- JP
- Japan
- Prior art keywords
- conductive pattern
- wiring board
- lead frame
- deposited
- feature
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987127769U JPH0735404Y2 (ja) | 1987-08-21 | 1987-08-21 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987127769U JPH0735404Y2 (ja) | 1987-08-21 | 1987-08-21 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6433752U true JPS6433752U (cs) | 1989-03-02 |
| JPH0735404Y2 JPH0735404Y2 (ja) | 1995-08-09 |
Family
ID=31380493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987127769U Expired - Lifetime JPH0735404Y2 (ja) | 1987-08-21 | 1987-08-21 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0735404Y2 (cs) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61136249A (ja) * | 1984-12-06 | 1986-06-24 | Nec Kansai Ltd | ハイブリツドｉｃ |
-
1987
- 1987-08-21 JP JP1987127769U patent/JPH0735404Y2/ja not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61136249A (ja) * | 1984-12-06 | 1986-06-24 | Nec Kansai Ltd | ハイブリツドｉｃ |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0735404Y2 (ja) | 1995-08-09 |