JPS6436136A - Multiplex signal separating circuit - Google Patents
Multiplex signal separating circuitInfo
- Publication number
- JPS6436136A JPS6436136A JP19181587A JP19181587A JPS6436136A JP S6436136 A JPS6436136 A JP S6436136A JP 19181587 A JP19181587 A JP 19181587A JP 19181587 A JP19181587 A JP 19181587A JP S6436136 A JPS6436136 A JP S6436136A
- Authority
- JP
- Japan
- Prior art keywords
- ram
- rom
- multiplex signal
- separation
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000926 separation method Methods 0.000 abstract 4
Landscapes
- Time-Division Multiplex Systems (AREA)
Abstract
PURPOSE:To reduce the number of components of the titled separating circuit by adopting software processing for the processing of separating and outputting a multiplex signal, and writing the software into a ROM. CONSTITUTION:The titled circuit consists of a RAM 3 storing data in terms of multiplex signals inputted in the past, a ROM 4 outputting separation signals 108-112 from a multiplex signal 101, a separation address 102 and outputs 103-107 of the RAM 3, a filp-flop 5 adjusting an output timing of the separation signals 108-112, and a buffer 6 delivering its output to the RAM 3. The ROM 4 rewrites a data corresponding to the separation address 102 among data inputted from the RAM 3 and outputs a data representing a new operating state of the line. Since the processing executed by using lots of gate circuits in a conventional circuit is implemented by employing simple hardware such as a ROM and a RAM in such a way, the number of components is reduced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19181587A JPH071880B2 (en) | 1987-07-30 | 1987-07-30 | Multiple signal separation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19181587A JPH071880B2 (en) | 1987-07-30 | 1987-07-30 | Multiple signal separation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6436136A true JPS6436136A (en) | 1989-02-07 |
| JPH071880B2 JPH071880B2 (en) | 1995-01-11 |
Family
ID=16280984
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19181587A Expired - Lifetime JPH071880B2 (en) | 1987-07-30 | 1987-07-30 | Multiple signal separation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH071880B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7922473B2 (en) | 2004-05-05 | 2011-04-12 | Fabio Perini S.P.A. | Roller with interchangeable sleeve for embossing units and embossing units comprising said roller |
-
1987
- 1987-07-30 JP JP19181587A patent/JPH071880B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7922473B2 (en) | 2004-05-05 | 2011-04-12 | Fabio Perini S.P.A. | Roller with interchangeable sleeve for embossing units and embossing units comprising said roller |
| JP4857265B2 (en) * | 2004-05-05 | 2012-01-18 | フアビオ・ペリニ・ソシエタ・ペル・アチオーニ | Roller with replaceable sleeve for embossing unit and embossing unit with said roller |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH071880B2 (en) | 1995-01-11 |
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