JPS6453396A - Output buffer circuit - Google Patents

Output buffer circuit

Info

Publication number
JPS6453396A
JPS6453396A JP62210683A JP21068387A JPS6453396A JP S6453396 A JPS6453396 A JP S6453396A JP 62210683 A JP62210683 A JP 62210683A JP 21068387 A JP21068387 A JP 21068387A JP S6453396 A JPS6453396 A JP S6453396A
Authority
JP
Japan
Prior art keywords
level
output
circuit
data signal
prescribed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62210683A
Other languages
Japanese (ja)
Inventor
Yoshihiko Okihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62210683A priority Critical patent/JPS6453396A/en
Publication of JPS6453396A publication Critical patent/JPS6453396A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Landscapes

  • Electronic Switches (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To accelerate an operation and to reduce power consumption, by providing a level setting circuit to set an output data signal once at a prescribed level between an 'H' level and an 'L' level. CONSTITUTION:A circuit 9 to set the output data signal at the prescribed level between the 'H' level and the 'L' level before outputting data is provided. The level setting circuit 9 sets the output data signal at the prescribed level between the 'H' level and the 'L' level before outputting the data by equalizing the input and the output of an inversion circuit 11 which inputs the NOT of the output of a sense amplifier 1 transiently by a delayed pulse signal from an address change detection circuit 8. In such a way, it is possible to perform data output at high speed and also, to save a current on the level setting circuit 9 at minimum.
JP62210683A 1987-08-25 1987-08-25 Output buffer circuit Pending JPS6453396A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62210683A JPS6453396A (en) 1987-08-25 1987-08-25 Output buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62210683A JPS6453396A (en) 1987-08-25 1987-08-25 Output buffer circuit

Publications (1)

Publication Number Publication Date
JPS6453396A true JPS6453396A (en) 1989-03-01

Family

ID=16593379

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62210683A Pending JPS6453396A (en) 1987-08-25 1987-08-25 Output buffer circuit

Country Status (1)

Country Link
JP (1) JPS6453396A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0574161A (en) * 1990-01-04 1993-03-26 Motorola Inc Integrated circuit memory
US6777986B2 (en) 1994-11-15 2004-08-17 Renesas Technology Corp. Data output circuit with reduced output noise

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0574161A (en) * 1990-01-04 1993-03-26 Motorola Inc Integrated circuit memory
US6777986B2 (en) 1994-11-15 2004-08-17 Renesas Technology Corp. Data output circuit with reduced output noise
US6975147B2 (en) 1994-11-15 2005-12-13 Renesas Technology Corp. Data output circuit with reduced output noise

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