JPS6436349A - Address developing circuit - Google Patents

Address developing circuit

Info

Publication number
JPS6436349A
JPS6436349A JP19237487A JP19237487A JPS6436349A JP S6436349 A JPS6436349 A JP S6436349A JP 19237487 A JP19237487 A JP 19237487A JP 19237487 A JP19237487 A JP 19237487A JP S6436349 A JPS6436349 A JP S6436349A
Authority
JP
Japan
Prior art keywords
register
data
address
word
modification
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19237487A
Other languages
Japanese (ja)
Inventor
Shuichi Hanatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19237487A priority Critical patent/JPS6436349A/en
Publication of JPS6436349A publication Critical patent/JPS6436349A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To easily execute address development, by holding the copy of the content of a universal register, setting 0 data on at least one of the words in advance, and reading out the 0 data when the address development without performing register modification is designated by an instruction word. CONSTITUTION:An index register 1 holds the 0 data in its word 0, and also, holds the copy of the content of the universal register, and performs index register modification. A base register 2 holds the 0 data in its word 0, and performs base register modification. Instruction register 3-5 hold displacement parts. An address adder 6 adds the content of the index register 1, that of the base register 2, and that of the instruction registers 3-5, and performs the address development. And when the address development without performing the register modification is designated by the instruction word, the address development can be easily performed by reading out the 0 data.
JP19237487A 1987-07-31 1987-07-31 Address developing circuit Pending JPS6436349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19237487A JPS6436349A (en) 1987-07-31 1987-07-31 Address developing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19237487A JPS6436349A (en) 1987-07-31 1987-07-31 Address developing circuit

Publications (1)

Publication Number Publication Date
JPS6436349A true JPS6436349A (en) 1989-02-07

Family

ID=16290226

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19237487A Pending JPS6436349A (en) 1987-07-31 1987-07-31 Address developing circuit

Country Status (1)

Country Link
JP (1) JPS6436349A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5432117A (en) * 1993-06-11 1995-07-11 Rohm Co., Ltd. Method of producing semiconductor device
US5702978A (en) * 1996-04-30 1997-12-30 Vlsi Technology, Inc. Sloped silicon nitride etch for smoother field oxide edge

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5432117A (en) * 1993-06-11 1995-07-11 Rohm Co., Ltd. Method of producing semiconductor device
US5702978A (en) * 1996-04-30 1997-12-30 Vlsi Technology, Inc. Sloped silicon nitride etch for smoother field oxide edge

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