JPS643734A - Multiplication circuit - Google Patents

Multiplication circuit

Info

Publication number
JPS643734A
JPS643734A JP62158728A JP15872887A JPS643734A JP S643734 A JPS643734 A JP S643734A JP 62158728 A JP62158728 A JP 62158728A JP 15872887 A JP15872887 A JP 15872887A JP S643734 A JPS643734 A JP S643734A
Authority
JP
Japan
Prior art keywords
multiplication
bytes
word length
output
basic word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62158728A
Other languages
Japanese (ja)
Inventor
Yuji Yoshida
Shigeharu Matsuzaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62158728A priority Critical patent/JPS643734A/en
Publication of JPS643734A publication Critical patent/JPS643734A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To realize the high-speed multiplication processing by using one of four multipliers for basic word length to perform the multiplication of the basic word length and then using all of these four multipliers for multiplication of the double word length respectively. CONSTITUTION:An adder 50 is used only for multiplication of the 8-bite data and serves as a 3-input addition circuit which adds the partial products P1-P4 received from multiplication units 1-4 respectively with proper digit matching. The output of the 3-input adder 50 is set at registers 61-63 respectively. At the same time, a partial product P4L is set as it is at a register 64. The output selection circuits 81 and 82 select the output of the unit 1 with the (4X4 bytes)- multiplication and then the outputs of registers 61-64 with the (8X8 bytes)- multiplication. While the output selection circuits 71 and 72 selects and reads out both higher and lower level 8 bytes respectively of 16 bytes of the (8X8 bytes)-multiplication. The multiplication result of the unit 1 is selected by both circuits 81 and 82 with multiplication of the basic word length and then delivered directly. Thus the time needed for the multiplication processing can be shortened.
JP62158728A 1987-06-25 1987-06-25 Multiplication circuit Pending JPS643734A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62158728A JPS643734A (en) 1987-06-25 1987-06-25 Multiplication circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62158728A JPS643734A (en) 1987-06-25 1987-06-25 Multiplication circuit

Publications (1)

Publication Number Publication Date
JPS643734A true JPS643734A (en) 1989-01-09

Family

ID=15678036

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62158728A Pending JPS643734A (en) 1987-06-25 1987-06-25 Multiplication circuit

Country Status (1)

Country Link
JP (1) JPS643734A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6038582A (en) * 1996-10-16 2000-03-14 Hitachi, Ltd. Data processor and data processing system
USRE44697E1 (en) 1998-02-27 2014-01-07 Mosaid Technologies Incorporated Encryption processor with shared memory interconnect

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60205746A (en) * 1984-03-30 1985-10-17 Toshiba Corp Array multiplier

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60205746A (en) * 1984-03-30 1985-10-17 Toshiba Corp Array multiplier

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6038582A (en) * 1996-10-16 2000-03-14 Hitachi, Ltd. Data processor and data processing system
US6243732B1 (en) 1996-10-16 2001-06-05 Hitachi, Ltd. Data processor and data processing system
US6327605B2 (en) 1996-10-16 2001-12-04 Hitachi, Ltd. Data processor and data processing system
USRE44697E1 (en) 1998-02-27 2014-01-07 Mosaid Technologies Incorporated Encryption processor with shared memory interconnect

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