JPS643749A - Logical simulation processor - Google Patents

Logical simulation processor

Info

Publication number
JPS643749A
JPS643749A JP15999487A JP15999487A JPS643749A JP S643749 A JPS643749 A JP S643749A JP 15999487 A JP15999487 A JP 15999487A JP 15999487 A JP15999487 A JP 15999487A JP S643749 A JPS643749 A JP S643749A
Authority
JP
Japan
Prior art keywords
accesses
event
arbiter
pipeline
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15999487A
Other languages
Japanese (ja)
Inventor
Hajime Asano
Yasuyuki Kanazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP15999487A priority Critical patent/JPS643749A/en
Publication of JPS643749A publication Critical patent/JPS643749A/en
Pending legal-status Critical Current

Links

Landscapes

  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To perform the logical simulation at a high speed by using a mechanism which measures the fullness of a pipeline and an arbiter which can change the arbitrating function for two accesses to registration and extraction against an event memory based on the measuring result of said measuring mechanism. CONSTITUTION:The registration of events and the extraction of events are available for accesses to an event memory 7 and these two accesses must be carried out exclusively to each other. Here an arbiter 26 arbitrates those two accesses. The arbiter 26 permits unconditionally one of both accesses as long as only said access has a request and then gives the relevant access to the memory 7. When two access requests are received at one time, one of both accesses is permitted with preference in case a full signal 36 is false, i.e., a pipeline is not filled and as long as an event extracting request lasts. While an event is registered with preference if the signal 36 is true, i.e., the pipeline is filled.
JP15999487A 1987-06-26 1987-06-26 Logical simulation processor Pending JPS643749A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15999487A JPS643749A (en) 1987-06-26 1987-06-26 Logical simulation processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15999487A JPS643749A (en) 1987-06-26 1987-06-26 Logical simulation processor

Publications (1)

Publication Number Publication Date
JPS643749A true JPS643749A (en) 1989-01-09

Family

ID=15705679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15999487A Pending JPS643749A (en) 1987-06-26 1987-06-26 Logical simulation processor

Country Status (1)

Country Link
JP (1) JPS643749A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5814257A (en) * 1981-07-17 1983-01-27 Fujitsu Ltd Data processor for logical simulation
JPS6299827A (en) * 1985-10-28 1987-05-09 Hitachi Ltd Buffer control method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5814257A (en) * 1981-07-17 1983-01-27 Fujitsu Ltd Data processor for logical simulation
JPS6299827A (en) * 1985-10-28 1987-05-09 Hitachi Ltd Buffer control method

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