JPS643769A - Memory access system - Google Patents

Memory access system

Info

Publication number
JPS643769A
JPS643769A JP62159352A JP15935287A JPS643769A JP S643769 A JPS643769 A JP S643769A JP 62159352 A JP62159352 A JP 62159352A JP 15935287 A JP15935287 A JP 15935287A JP S643769 A JPS643769 A JP S643769A
Authority
JP
Japan
Prior art keywords
memory
memories
processor
write
given
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62159352A
Other languages
Japanese (ja)
Inventor
Masanori Hirano
Takuya Hiramatsu
Seijiro Tajima
Haruo Kohama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP62159352A priority Critical patent/JPS643769A/en
Publication of JPS643769A publication Critical patent/JPS643769A/en
Pending legal-status Critical Current

Links

Landscapes

  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)
  • Storage Device Security (AREA)

Abstract

PURPOSE:To relieve the deterioration in the performance due to memory contention and to smooth the memory access by decentralizing a memory readout access from plural processors in using memories of M-multiple constitution by plural processors. CONSTITUTION:In applying memory write from a processor 1, a write command is given to memories 3, 4 via a signal line 17 and a write address A and a write data WD are given to the memories 3, 4 via an information bus 16. In case of the memory call from the processor 1, a readout command signal and the address A are sent to the memories 3, 4 via the signal line 18. Then the ID of an ID register 5 is outputted and checked by comparator circuits 11, 12 and when the ID of the processor 1 and the memory 3 are coincident, the output of the circuit 11 is set and a readout command is given to the memory 3 via an AND gate 13, etc. Moreover, in the memory access of a processor 2, the data is read out from the memory 4 and the deterioration in the performance due to memory contention is reduced and the memory access is smoothed.
JP62159352A 1987-06-26 1987-06-26 Memory access system Pending JPS643769A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62159352A JPS643769A (en) 1987-06-26 1987-06-26 Memory access system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62159352A JPS643769A (en) 1987-06-26 1987-06-26 Memory access system

Publications (1)

Publication Number Publication Date
JPS643769A true JPS643769A (en) 1989-01-09

Family

ID=15691969

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62159352A Pending JPS643769A (en) 1987-06-26 1987-06-26 Memory access system

Country Status (1)

Country Link
JP (1) JPS643769A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57101958A (en) * 1980-12-16 1982-06-24 Fujitsu Ltd Memory address extension system
JPS6047629A (en) * 1983-08-24 1985-03-15 高橋　丈夫 Continuous rat trap
JPS61248153A (en) * 1985-04-25 1986-11-05 Fujitsu Ltd Memory access controlling system in multiprocessor system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57101958A (en) * 1980-12-16 1982-06-24 Fujitsu Ltd Memory address extension system
JPS6047629A (en) * 1983-08-24 1985-03-15 高橋　丈夫 Continuous rat trap
JPS61248153A (en) * 1985-04-25 1986-11-05 Fujitsu Ltd Memory access controlling system in multiprocessor system

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