JPS643780A - Access system for memory - Google Patents

Access system for memory

Info

Publication number
JPS643780A
JPS643780A JP15785287A JP15785287A JPS643780A JP S643780 A JPS643780 A JP S643780A JP 15785287 A JP15785287 A JP 15785287A JP 15785287 A JP15785287 A JP 15785287A JP S643780 A JPS643780 A JP S643780A
Authority
JP
Japan
Prior art keywords
address
memory
cpu
selector
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15785287A
Other languages
Japanese (ja)
Inventor
Yutaka Udagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP15785287A priority Critical patent/JPS643780A/en
Priority to DE3885945T priority patent/DE3885945T2/en
Priority to EP88305704A priority patent/EP0296835B1/en
Publication of JPS643780A publication Critical patent/JPS643780A/en
Priority to US07/582,009 priority patent/US5323488A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To efficiently use a memory by designating an addressing from a CPU to the memory as to whether it is applied by a two-dimension address or a linear address so as to adopt the address system corresponding to the characteristic of data. CONSTITUTION:When a CPU 1 accesses the memory 6 in the two-dimension address, a switching signal to select an A input for a selector 44 is set to an address selection register 42. Then two-dimension X, Y addresses are set to an X address 40 and a Y address 41, they are converted into the linear address of the memory 6 by an address converter 43 and inputted to the A input of the selector 44. On the other hand, the address data of an address bus 49 of the CPU 1 is connected to a B input of the selector 44 and when the selector 44 selects the B input, the address space of the memory 6 is included as a part of the address space of the CPU 1 to allow the CPU 1 to access the memory 6 by the linear address. Thus, the address system corresponding to the data characteristic is selected and the memory 6 is used efficiently.
JP15785287A 1987-06-24 1987-06-26 Access system for memory Pending JPS643780A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP15785287A JPS643780A (en) 1987-06-26 1987-06-26 Access system for memory
DE3885945T DE3885945T2 (en) 1987-06-24 1988-06-22 Color printer.
EP88305704A EP0296835B1 (en) 1987-06-24 1988-06-22 Colour printer apparatus
US07/582,009 US5323488A (en) 1987-06-24 1990-09-14 Memory access method and circuit in which access timing to a memory is divided into N periods to be accessed from N access request sources

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15785287A JPS643780A (en) 1987-06-26 1987-06-26 Access system for memory

Publications (1)

Publication Number Publication Date
JPS643780A true JPS643780A (en) 1989-01-09

Family

ID=15658779

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15785287A Pending JPS643780A (en) 1987-06-24 1987-06-26 Access system for memory

Country Status (1)

Country Link
JP (1) JPS643780A (en)

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