JPS643959U - - Google Patents
Info
- Publication number
- JPS643959U JPS643959U JP9822287U JP9822287U JPS643959U JP S643959 U JPS643959 U JP S643959U JP 9822287 U JP9822287 U JP 9822287U JP 9822287 U JP9822287 U JP 9822287U JP S643959 U JPS643959 U JP S643959U
- Authority
- JP
- Japan
- Prior art keywords
- data
- trace
- memory
- microprocessor
- address counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図は本考案の動作原理を示す図、第２図は
トレース・メモリへの記録状態を示す説明図、第
３図は本考案に係るマイクロプロセツサ・アナラ
イザの一実施例を示す構成図、第４図はブレーク
時の不要データのサンプル状態を説明するための
図、第５図はＳＴＵＢを実行した場合の不要デー
タのサンプル状態を説明するための図である。
１…ターゲツトμＰ、２…ＳＴＵＢ検出回路、
３…メモリ・アドレス・カウンタ、４…タイミン
グ回路、５…トレース・メモリ、６…コントロー
ルＣＰＵ、７〜１０…３ステート・バツフア、１
１…ターゲツトμＰバス、１２…コントロールＣ
ＰＵバス、１３…表示装置。
FIG. 1 is a diagram showing the operating principle of the present invention, FIG. 2 is an explanatory diagram showing the state of recording in the trace memory, and FIG. 3 is a configuration diagram showing an embodiment of the microprocessor analyzer according to the present invention. , FIG. 4 is a diagram for explaining the sample state of unnecessary data at the time of a break, and FIG. 5 is a diagram for explaining the sample state of unnecessary data when STUB is executed. 1...Target μP, 2...STUB detection circuit,
3...Memory address counter, 4...Timing circuit, 5...Trace memory, 6...Control CPU, 7-10...3-state buffer, 1
1...Target μP bus, 12...Control C
PU bus, 13...Display device.
Claims (1)
予め設定された条件に一致した場合、トレース・
メモリへの記録動作を制御すると共にメモリ・ア
ドレス・カウンタの計数動作を制御する信号を出
力するＳＴＵＢ検出回路と、ターゲツト・マイク
ロプロセツサの出力するバス・データからバスサ
イクルに同期したサンプル・クロツクを前記メモ
リ・アドレス・カウンタに与えるタイミング回路
と、前記メモリ・アドレス・カウンタの出力する
アドレスに前記ターゲツト・マイクロプロセツサ
のバス・データを記録するトレース・メモリを備
え、データをサンプルして順次トレース・メモリ
に記憶し、得られたトレース・データを参照して
ターゲツト・マイクロプロセツサの動作を解析す
ることができるように構成されたマイクロプロセ
ツサ・アナライザにおいて、 前記ターゲツト・マイクロプロセツサにブレー
クがかかつた場合、トレース・メモリに記憶され
たトレース・データ中、ターゲツト・マイクロプ
ロセツサの種類および割り込みの種類に応じてブ
レーク・ポイントから所定数のデータだけ遡つて
特定ビツトの内容を書き換える処理を行う手段と
、 前記トレース・データの表示の際には、前記特
定ビツトが書き換えられたトレース・データにつ
いては表示の対象から除外する手段 を具備したことを特徴とするマイクロプロセツ
サ・アナライザ。[Claims for Utility Model Registration] If the bus signal of the target microprocessor matches a preset condition, the trace
A STUB detection circuit that outputs a signal that controls the recording operation to the memory and the counting operation of the memory address counter, and a sample clock that is synchronized with the bus cycle from the bus data output from the target microprocessor. The memory address counter includes a timing circuit that supplies data to the memory address counter, and a trace memory that records bus data of the target microprocessor at the address output from the memory address counter, and samples the data and sequentially traces the data. In a microprocessor analyzer configured to be able to analyze the operation of a target microprocessor by referring to trace data stored in a memory and obtained, a break occurs in the target microprocessor. If this occurs, a process is performed to rewrite the contents of specific bits in the trace data stored in the trace memory by going back a predetermined number of data from the break point, depending on the type of target microprocessor and the type of interrupt. A microprocessor analyzer comprising: means for excluding trace data in which the specific bit has been rewritten from display when displaying the trace data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9822287U JPS643959U (en) | 1987-06-26 | 1987-06-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9822287U JPS643959U (en) | 1987-06-26 | 1987-06-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS643959U true JPS643959U (en) | 1989-01-11 |
Family
ID=31324293
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9822287U Pending JPS643959U (en) | 1987-06-26 | 1987-06-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS643959U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02267416A (en) * | 1989-04-07 | 1990-11-01 | Matsushita Electric Ind Co Ltd | liquid fuel combustion equipment |
-
1987
- 1987-06-26 JP JP9822287U patent/JPS643959U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02267416A (en) * | 1989-04-07 | 1990-11-01 | Matsushita Electric Ind Co Ltd | liquid fuel combustion equipment |
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