JPS644113A - Oscillating circuit - Google Patents

Oscillating circuit

Info

Publication number
JPS644113A
JPS644113A JP62159323A JP15932387A JPS644113A JP S644113 A JPS644113 A JP S644113A JP 62159323 A JP62159323 A JP 62159323A JP 15932387 A JP15932387 A JP 15932387A JP S644113 A JPS644113 A JP S644113A
Authority
JP
Japan
Prior art keywords
trs
circuit
outputted
amplifier circuit
energized states
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62159323A
Other languages
Japanese (ja)
Inventor
Akira Kimura
Michiya Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62159323A priority Critical patent/JPS644113A/en
Publication of JPS644113A publication Critical patent/JPS644113A/en
Pending legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To eliminate the effect of noise caused in an inverse amplifier circuit by outputting an oscillation signal from an output terminal of the inverse amplifier circuit to a semiconductor integrated circuit of the next stage via a switch circuit. CONSTITUTION:Oscillation signals whose phases are opposite to each other are outputted from two output terminals 11 of the inverse amplifier circuit 1 normally, P-channel MOS transistors (TRs) Q1, Q2 or N-channel MOS TRs Q3, Q4 are made into energized states and a shaped clock signal is outputted from an inverter 2. On the other hand, if noise is caused in the circuit 1 and the signals from both the terminals 11 are in phase and one of the TRs Q1, Q2 and one of the TRs Q3, Q4 are made into non-energized states, the level between the TRs Q2 and Q3 is kept to a level when the TRs Q1, Q2 or Q3, Q4 are made into energized states previously. Thus, a clock signal not susceptible to the effect of noise caused in the circuit 1 is outputted from the inverter 2.
JP62159323A 1987-06-25 1987-06-25 Oscillating circuit Pending JPS644113A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62159323A JPS644113A (en) 1987-06-25 1987-06-25 Oscillating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62159323A JPS644113A (en) 1987-06-25 1987-06-25 Oscillating circuit

Publications (1)

Publication Number Publication Date
JPS644113A true JPS644113A (en) 1989-01-09

Family

ID=15691296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62159323A Pending JPS644113A (en) 1987-06-25 1987-06-25 Oscillating circuit

Country Status (1)

Country Link
JP (1) JPS644113A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6459327B1 (en) * 1991-12-09 2002-10-01 Oki Electric Industry Co., Ltd. Feedback controlled substrate bias generator
DE112012005314B4 (en) * 2011-12-20 2016-07-28 Analog Devices Inc. Oscillator regeneration device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6459327B1 (en) * 1991-12-09 2002-10-01 Oki Electric Industry Co., Ltd. Feedback controlled substrate bias generator
DE112012005314B4 (en) * 2011-12-20 2016-07-28 Analog Devices Inc. Oscillator regeneration device

Similar Documents

Publication Publication Date Title
TW332290B (en) Semiconductor integrated circuit
KR890004212B1 (en) Complementary logic circuit
KR940000253Y1 (en) Nmos exclusive or gate circuit
EP0685807A4 (en) Semiconductor integrated circuit.
EP0376065A3 (en) Semiconductor memory integrated circuit
KR950007287A (en) Delay Circuit for Digital Signal Processing
KR920013441A (en) Semiconductor integrated circuit
JPS644113A (en) Oscillating circuit
TW367653B (en) Division circuit of 4/5
TW257906B (en) ECL differential multiplexing circuit
CH638656B (en) SEMICONDUCTOR PLATE CONSTITUTING AN ELECTRONIC WATCH PART CIRCUIT.
EP0228216A3 (en) Differential amplifier
EP0114061A3 (en) Semiconductor device having cmos structures
CH641001B (en) ELECTRONIC WATCH PART, ESPECIALLY ELECTRONIC BRACELET WATCH.
JPS5648721A (en) Integrated circuit
EP0274243A3 (en) Improved oscillator circuit utilizing multiple semiconductor devices
US4845444A (en) Frequency doubling crystal oscillator via a current mirror
JPS6442720A (en) Clock generating circuit
KR930001172Y1 (en) CMOS logic integrated circuit
JPS648715A (en) Logic circuit device
JPH01228214A (en) Semiconductor integrated circuit
KR930004892Y1 (en) Latching circuit
EP0130376A3 (en) Low-voltage dual-phase logic circuit
JPS5783931A (en) Output buffer circuit
EP0661812A1 (en) Interface TTL/CMOS circuit with temperature and supply voltage independent threshold level