JPS644200B2 - - Google Patents

Description

[Detailed description of the invention]

[Technical Field of the Invention] The present invention relates to a waveform generator that generates waveforms using digital technology. [Background of the Invention] With the advancement of digital technology, it has become possible to generate waveform information in a digital circuit and convert the waveform information into an analog signal using a digital-to-analog converter. Such technology is also used when generating sounds or generating sound effects in electronic game devices. The present applicant has already made a new proposal as a technology related to such technology (Japanese Patent Application No. 57-
221266). This proposal has a storage means that stores waveform information such as a sine wave, and supplies an address signal for it as a modified address signal whose rate changes within one cycle of the waveform.As a result, the frequency spectrum of the waveform is smoothed. It was possible to generate waveforms such as rectangular waves, sawtooth waves, etc. from which high-frequency components of the signal spectrum were removed. The present invention is related to this prior art. [Object of the Invention] It is an object of the present invention to provide a waveform generation device that generates a waveform having a frequency spectrum that has never been seen before and that smoothly changes the frequency spectrum. [Key Points of the Invention] One cycle of the waveform is divided into multiple cycles, for example, two cycles, depending on the modulation information.
The waveform generator is configured to modify and apply an address signal to the storage means so that the waveform information for one period is read out from the storage means in two blocks with different time widths in each block. [Embodiment] An embodiment in which the present invention is applied to an electronic musical instrument will be described in detail below with reference to the drawings. FIG. 1 shows the block circuit configuration. In the figure, 1 is a keyboard, the output of which is a frequency information generating circuit 2.
is supplied to generate frequency information (phase angle information) corresponding to the operation key. The output is then accumulated in the phase angle calculation circuit 3 to specify the phase angle of the waveform. The output of this phase angle calculation circuit 3 is supplied as an address signal to the N input terminal of the waveform generation circuit 4, and is also fed back to its own input terminal and used for the above-mentioned accumulation. Further, from the keyboard 1, a signal indicating whether a key is on or off, or a signal indicating a key range of an operating key is applied to the modulation signal generating circuit 5. Therefore, the modulation signal generation circuit 5 outputs, for example, a modulation signal that changes over time or a modulation signal that changes depending on the key range, and supplies it to the addition circuit 6. Furthermore, a control signal output, such as a volume, which can be used by the performer and which can be controlled to vary the modulation conditions, is also applied to the adder circuit 6. The output of the adder circuit 6 is then supplied to the M input terminal of the waveform generating circuit 4 as a modulation signal. In the waveform generation circuit 4, one synchronization is divided into, for example, two blocks by the modulation signal, each block generates one period of the waveform, and the waveform information is sent from the output terminal and sent to the envelope multiplication circuit. Supply to 7. The keyboard 1 further causes an envelope control signal generation circuit 8 to generate an envelope control signal, for example, an envelope waveform signal having attack, decay, sustain, and release parts. Then, the envelope control signal is supplied to the envelope multiplication circuit 7, multiplied by the waveform information from the waveform generation circuit, and the envelope-controlled waveform information is output to the D/A converter and converted into an analog signal. , appropriately amplified and output from a speaker. FIG. 2 shows details of the waveform generation circuit 4 shown in FIG. 1, and the N input terminal receives 12-bit address signals N ₀ -
N ₁₁ is supplied from the phase angle calculation circuit 3, and its address signals N ₀ to _{N 11} are supplied to the A input terminal A ₀ of the divider 41.
~A ₁₁ through gates 42-0 to 42-11. Note that these gates 42-0 to 42-
The symbol 11 represents an exclusive OR gate as shown in FIG. Further, the address signals N ₀ -N ₁₁ are supplied to A input terminals A ₀ -A ₁₁ of the comparator 43. The B input terminals B ₀ to B ₁₀ of this comparator 43 receive a modulation signal M ₀ input from the M input terminal of the waveform generation circuit 4.
~ _M10 is supplied. Further, a ground level, ie, "0" signal is supplied to the input terminal _B11 of the most significant bit. Then, the comparator 43 compares the magnitude of the signal input to the A input terminal and the signal input to the B input terminal, and determines that the modulation signal input to the B input terminal is smaller than the address signal input to the A input terminal. In case,
Outputs “1” signal. Conversely, if the modulation signal is greater than the address signal, a "0" signal is output. Therefore, as will be described later, in one cycle of the waveform, up to the address specified by the modulation signal, that is, during the first half block of the waveform, the comparator 43
outputs a "0" signal, and during the latter half of the block, the comparator 43 outputs a "1" signal. The output of the comparator 43 is applied to the gates 44-0 to 42-11 as well as the gates 42-0 to 42-11.
0 to 44-11, 45-0 to 45-11. That is, the gates 44-0 to 44-10 receive the modulation signals M ₀ to 44-10 input from the M input terminals.
_M10 is supplied, and the gate 44-11 is supplied with a ground level, that is, a "0" signal.
It is controlled whether or not to invert the logic level of the input signal at the output of the comparator 43 and output it. The output modulated signal (or its inverted signal) is supplied to the B input terminals B ₀ to B ₁₁ of the divider 41 via the gates 44-0 to 44-11. Then, the divider 41 divides the address signal (or its inverted signal) inputted to the A input terminal by the modulation signal (or its inverted signal) inputted to the B input terminal, and divides the operation result signal into D
Output from output terminals _D0 to _D11 . The output signals are then supplied to the address input terminals A ₀ -A ₁₁ of the ROM 46 via the gates 45-1 - 45-11 described above. This ROM 46 stores a sine wave or a cosine wave. In this embodiment, as will be described later, it is assumed that one cycle of a cosine wave is stored, but for example, such waveform information for 1/2 cycle or 1/4 cycle is stored, and the waveform One cycle of waveform information may be read out by inverting the logic level of the information or inverting and applying an address signal. Waveform information is output from output terminal 0 (0 ₀ to 0 ₁₀ ) of this ROM 46, and output terminal O of the waveform generation circuit 4.
and sent to the envelope multiplication circuit 7. Next, waveform generation in this embodiment will be explained with reference to FIG. In FIG. 4, arrow A indicates a cosine wave stored in the ROM 46, and steps 0 to 4095 (=2 ¹² −
1). Assume now that the modulated signals M ₀ to _{M 10} given from the M input end take any value between 0 and 2047 (2 ¹¹ -1). That is, if this period is T, then the modulated signal M satisfies 0<M<T/2. At that time, the phase angle calculation circuit 3 of FIG.
The address signal N supplied from the address signal N changes from 0 to 4095, but as shown in FIG. ” signal is output, and as a result, the address signal N1,
A modulation signal M is directly supplied. Therefore, divider 4
1 outputs the calculation result N1/M·2 ¹² =N1/M·T. By the way, this value N1/M·T=L1 corresponds to the address signal L1 shown in FIG. Similarly, when the address signal N takes the value N2 that satisfies the condition M<N<T, the comparator 4
3 outputs a “1” signal, and as a result, gate 42
-0~42-11,44-0~44-11,45
-0 to 45-11 respectively invert the input signals and output them, resulting in gates 45-0 to 45-11.
The output of 45-11 is

[Formula] Takes the value. Note that the bar means logical inversion. If this value is designated as L2, it will be understood that this corresponds to the address of L2 shown in FIG. That is, =T-M, 2=T-N2, 2=T-
Since L2, the output of the divider 41 is

Take [formula] and convert it into gate 45-0 Since it will be reversed at ~45-11,

[Formula] and Become. Therefore,

[Formula] becomes. Then, if we invert the logic levels on both sides, we get

〔Effect of the invention〕

As described above, the present invention has a simple configuration and can generate a waveform signal having a frequency spectrum that has never been seen before, and can smoothly change the frequency spectrum.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention; FIG. 1 is a block circuit diagram thereof, FIG. 2 is a detailed diagram of the waveform generation circuit of FIG. 1, FIG. 3 is a diagram for explaining the gate, and FIG. FIG. 4 is a diagram for explaining the output waveform signal, and FIGS. 5 to 9 are diagrams for explaining the relationship between the output waveform and the frequency spectrum according to this embodiment. 2... Frequency information generation circuit, 3... Phase angle calculation circuit, 4... Waveform generation circuit, 5... Modulation signal generation circuit, 41... Divider, 43... Comparator,
46...ROM.

Claims (1)

[Scope of Claims] 1. A storage means for storing waveform information representing at least a part of a sine wave or a cosine wave; and an output waveform to be generated in order to read out the waveform information stored in the storage means. address signal generating means for generating an address signal that corresponds to the frequency of the waveform and changes at a uniform rate over one cycle of the waveform; In order to read out at least two different periods in the period,
a modulation information generating means for generating modulation information specifying a switching phase of each cycle; the address signal from the address signal generating means and the modulation information from the modulation information generating means being supplied; modified address signal output means for outputting a modified address signal that reads out the waveform information one cycle at a time for each period specified by the modulation information while the address signal specifies one cycle of the waveform; By accessing the storage means in accordance with the modified address signal outputted from the address signal output means, the waveform information is generated one cycle at a time for each different period specified by the modulation information. A waveform generator comprising: an access means configured to obtain the output waveform using the output waveform; 2. The corrected address signal output means includes comparison means for comparing the address signal output from the address signal generation means and the modulation information output from the modulation information generation means, and a comparison result output of the comparison means. Accordingly, either the address signal or its inverted level signal is given to one end, and either the modulation information or its inverted level information is given to the other end,
division means configured to obtain the corrected address signal from the output terminal by dividing the input signal to the one terminal by the input signal to the other terminal;
The access means uses the modified address signal to modify the waveform while the address signal specifies from the first phase of one period of the sine wave or cosine wave to the phase specified by the modulation information. The waveform information is read by specifying the phase of one cycle, and one cycle of the waveform is read while the address signal specifies the phase from the phase specified by the modulation information to the final phase of one cycle of the waveform. 2. The waveform generator according to claim 1, wherein the waveform information is read out by specifying a phase of the waveform. 3. The waveform generator according to claim 1, wherein the modulation information generating means generates the modulation information that changes over time. 4. Claims characterized in that the address signal generating means generates phase angle information specifying the phase angle of the waveform as the address signal at a uniform rate corresponding to the frequency of the waveform to be generated. The waveform generator according to item 1.