JPS6447076U - - Google Patents
Info
- Publication number
- JPS6447076U JPS6447076U JP13998987U JP13998987U JPS6447076U JP S6447076 U JPS6447076 U JP S6447076U JP 13998987 U JP13998987 U JP 13998987U JP 13998987 U JP13998987 U JP 13998987U JP S6447076 U JPS6447076 U JP S6447076U
- Authority
- JP
- Japan
- Prior art keywords
- conductive foil
- connector
- pattern
- circuit board
- printed circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011888 foil Substances 0.000 claims description 8
- 230000037431 insertion Effects 0.000 claims 1
- 238000003780 insertion Methods 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 1
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Description
第１図は本考案の第１の実施例を示す平面図、
第２図は本考案の第２の実施例を示す平面図、第
３図は第１の従来例を示す平面図、第４図は第２
の従来例であるのＦＰＣの基本的構成を示す断面
図、第５図は第２の従来例を示す平面図である。
２１…リジツドプリント基板、２２，３２…コ
ネクタ部、２３，３３…コネクタパターン、２４
，３７…導箔ストリツプ、２５，３５…導箔露出
部、２６，３６…隣接導箔露出部との間隔、２７
…端子めつき用導体として使用する導箔露出部端
部、２８…絶縁性ベース、３１…ＦＰＣ、３８…
ベースフイルム、２９，３９…導体パターン、４
０…オーバレイフイルム。
FIG. 1 is a plan view showing a first embodiment of the present invention;
Fig. 2 is a plan view showing the second embodiment of the present invention, Fig. 3 is a plan view showing the first conventional example, and Fig. 4 is a plan view showing the second embodiment of the present invention.
FIG. 5 is a sectional view showing the basic structure of a conventional FPC, and FIG. 5 is a plan view showing a second conventional example. 21... Rigid printed circuit board, 22, 32... Connector part, 23, 33... Connector pattern, 24
, 37... Conductive foil strip, 25, 35... Conductive foil exposed portion, 26, 36... Distance between adjacent conductive foil exposed portion, 27
...Exposed end of conductive foil used as a conductor for terminal plating, 28...Insulating base, 31...FPC, 38...
Base film, 29, 39... conductor pattern, 4
0...Overlay film.
Claims (1)
ーンを露出させてコネクタへの差し込みを可能に
するコネクタ部を備えたプリント基板のパターン
構造において、前記コネクタパターンを形成する
各導箔露出部の少なくとも端縁部が内方の導箔ス
トリツプ巾よりも巾狭とされるとともに、導箔露
出部間隔が内方の導箔ストリツプ間隔よりも巾広
とされてなることを特徴とするプリント基板のパ
ターン構造。 In a pattern structure of a printed circuit board having a connector part that exposes a connector pattern formed at the end of an insulating base and enables insertion into the connector, at least the end of each conductive foil exposed part forming the connector pattern. A pattern structure of a printed circuit board, characterized in that the edge portion is narrower than the width of the inner conductive foil strip, and the interval between exposed conductive foil parts is wider than the interval between the inner conductive foil strips. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13998987U JPS6447076U (en) | 1987-09-16 | 1987-09-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13998987U JPS6447076U (en) | 1987-09-16 | 1987-09-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6447076U true JPS6447076U (en) | 1989-03-23 |
Family
ID=31403751
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13998987U Pending JPS6447076U (en) | 1987-09-16 | 1987-09-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6447076U (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7098479B1 (en) | 1990-12-25 | 2006-08-29 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
| US7115902B1 (en) | 1990-11-20 | 2006-10-03 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
| US7507615B2 (en) | 1990-11-09 | 2009-03-24 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing gate insulated field effect transistors |
| US7547915B2 (en) | 1994-06-09 | 2009-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having SiOxNy film |
| US7855106B2 (en) | 1991-08-26 | 2010-12-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5524856U (en) * | 1978-08-02 | 1980-02-18 |
-
1987
- 1987-09-16 JP JP13998987U patent/JPS6447076U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5524856U (en) * | 1978-08-02 | 1980-02-18 |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7507615B2 (en) | 1990-11-09 | 2009-03-24 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing gate insulated field effect transistors |
| US7115902B1 (en) | 1990-11-20 | 2006-10-03 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
| US7098479B1 (en) | 1990-12-25 | 2006-08-29 | Semiconductor Energy Laboratory Co., Ltd. | Electro-optical device and method for manufacturing the same |
| US7855106B2 (en) | 1991-08-26 | 2010-12-21 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
| US7547915B2 (en) | 1994-06-09 | 2009-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having SiOxNy film |
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