JPS6447120A - Noise elimination circuit - Google Patents

Noise elimination circuit

Info

Publication number
JPS6447120A
JPS6447120A JP20377287A JP20377287A JPS6447120A JP S6447120 A JPS6447120 A JP S6447120A JP 20377287 A JP20377287 A JP 20377287A JP 20377287 A JP20377287 A JP 20377287A JP S6447120 A JPS6447120 A JP S6447120A
Authority
JP
Japan
Prior art keywords
pulse signal
time width
pulse
eliminated
preset value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20377287A
Other languages
Japanese (ja)
Inventor
Mikio Hikino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP20377287A priority Critical patent/JPS6447120A/en
Publication of JPS6447120A publication Critical patent/JPS6447120A/en
Pending legal-status Critical Current

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  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To vary the time width of a noise pulse to be eliminated by providing a 1st circuit outputting a pulse signal having a time width in response to the time width of an input pulse signal and a 2nd circuit holding the input pulse signal and outputting the result. CONSTITUTION:A programmable counter 5 synchronously with an edge of an input pulse signal starts counting according to the input clock. When the count of a preset value is finished, a DFF 3 holds the state of the pulse signal synchronously therewith and outputs the result. A load signal is inputted at the same time and a preset value is present to the counter 5. Then the pulse time width of the output pulse signal of the counter 5 is set optionally through the combination of the clock period and the preset value. Thus, the noise pulse having a shorter time width than the pulse signal width is eliminated and the time width of the noise pulse to be eliminated is changed automatically.
JP20377287A 1987-08-17 1987-08-17 Noise elimination circuit Pending JPS6447120A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20377287A JPS6447120A (en) 1987-08-17 1987-08-17 Noise elimination circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20377287A JPS6447120A (en) 1987-08-17 1987-08-17 Noise elimination circuit

Publications (1)

Publication Number Publication Date
JPS6447120A true JPS6447120A (en) 1989-02-21

Family

ID=16479547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20377287A Pending JPS6447120A (en) 1987-08-17 1987-08-17 Noise elimination circuit

Country Status (1)

Country Link
JP (1) JPS6447120A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6392474B1 (en) 1999-09-07 2002-05-21 Bae Systems Information And Electronic Systems Integration Inc. Circuit for filtering single event effect (see) induced glitches

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6392474B1 (en) 1999-09-07 2002-05-21 Bae Systems Information And Electronic Systems Integration Inc. Circuit for filtering single event effect (see) induced glitches

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