JPS6448169A - Data communication system - Google Patents

Data communication system

Info

Publication number
JPS6448169A
JPS6448169A JP20543787A JP20543787A JPS6448169A JP S6448169 A JPS6448169 A JP S6448169A JP 20543787 A JP20543787 A JP 20543787A JP 20543787 A JP20543787 A JP 20543787A JP S6448169 A JPS6448169 A JP S6448169A
Authority
JP
Japan
Prior art keywords
outputted
processor
signal
output
fifo memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20543787A
Other languages
Japanese (ja)
Other versions
JP2711840B2 (en
Inventor
Koichi Aida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62205437A priority Critical patent/JP2711840B2/en
Publication of JPS6448169A publication Critical patent/JPS6448169A/en
Application granted granted Critical
Publication of JP2711840B2 publication Critical patent/JP2711840B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Complex Calculations (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To increase the pipeline speed by using the empty signal or the full flag of a first-in first-out (FIFO) memory as the ready signal of a digital signal processor. CONSTITUTION:A FIFO memory 2 for input which has a data output terminal MDO connected to a data input/output two-way port 11 of a digital signal processor 1 and a FIFO memory 3 for output which has a data input terminal MDI connected to said port 11 are provided. AND between a read signal R outputted from the processor 1 and an empty flag EF outputted from the FIFO memory 2 for input is operated by a logic circuit 4, and AND between a write signal W outputted from the processor 1 and a full flag FF outputted from the FIFO memory 3 for output is operated, and OR between them is outputted to the terminal of a ready signal RDY of the processor 1. Thus, the pipe-line speed is increased.
JP62205437A 1987-08-19 1987-08-19 Data transfer control device Expired - Fee Related JP2711840B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62205437A JP2711840B2 (en) 1987-08-19 1987-08-19 Data transfer control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62205437A JP2711840B2 (en) 1987-08-19 1987-08-19 Data transfer control device

Publications (2)

Publication Number Publication Date
JPS6448169A true JPS6448169A (en) 1989-02-22
JP2711840B2 JP2711840B2 (en) 1998-02-10

Family

ID=16506856

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62205437A Expired - Fee Related JP2711840B2 (en) 1987-08-19 1987-08-19 Data transfer control device

Country Status (1)

Country Link
JP (1) JP2711840B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0683578A (en) * 1992-03-13 1994-03-25 Internatl Business Mach Corp <Ibm> Processing system and data throughput control method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5213740A (en) * 1975-07-22 1977-02-02 Mitsubishi Electric Corp Information transmission system
JPS5247644A (en) * 1975-10-15 1977-04-15 Toshiba Corp Control method of information transmission
JPS59146380A (en) * 1983-02-10 1984-08-22 Matsushita Electric Ind Co Ltd digital signal processing device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5213740A (en) * 1975-07-22 1977-02-02 Mitsubishi Electric Corp Information transmission system
JPS5247644A (en) * 1975-10-15 1977-04-15 Toshiba Corp Control method of information transmission
JPS59146380A (en) * 1983-02-10 1984-08-22 Matsushita Electric Ind Co Ltd digital signal processing device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0683578A (en) * 1992-03-13 1994-03-25 Internatl Business Mach Corp <Ibm> Processing system and data throughput control method

Also Published As

Publication number Publication date
JP2711840B2 (en) 1998-02-10

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees