JPS6449344A - Loop back control system - Google Patents

Loop back control system

Info

Publication number
JPS6449344A
JPS6449344A JP20590487A JP20590487A JPS6449344A JP S6449344 A JPS6449344 A JP S6449344A JP 20590487 A JP20590487 A JP 20590487A JP 20590487 A JP20590487 A JP 20590487A JP S6449344 A JPS6449344 A JP S6449344A
Authority
JP
Japan
Prior art keywords
data
control
circuit
inputted
node number
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20590487A
Other languages
Japanese (ja)
Inventor
Toru Nakao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP20590487A priority Critical patent/JPS6449344A/en
Publication of JPS6449344A publication Critical patent/JPS6449344A/en
Pending legal-status Critical Current

Links

Landscapes

  • Selective Calling Equipment (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To simply attain control to execute loop back only with a specified receiving station from any station by providing a control data inserting means to insert a node number to designate a control code to set or cancel loop back control and a receiving point in which the loop back control is executed to transmitting data and a first node number detecting means to detect whether the node number of receiving data is zero or not. CONSTITUTION:Data I transmitted from a front step are inputted by a buffer 1 and converted to parallel data by a shift register 2. The inputted data converted to parallel data by the shift register 2 are inputted to comparing circuits 3 and 4, a decrement circuit 5 and a gate circuit 8. In the comparing circuit 4, whether the control code of the inputted data is coincident with control data given in advance or not is compared and when they are not coincident, an output terminal A=B is made low level. When the control code is coincident with the control data, the output terminal A=B is made high level and an enable terminal E of the decrement circuit 5 is turned on. Then, this circuit is operated. The decrement circuit 5 subtracts 1 from an inputted node number and outputs the result to a comparing circuit 6 and a gate circuit 7.
JP20590487A 1987-08-19 1987-08-19 Loop back control system Pending JPS6449344A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20590487A JPS6449344A (en) 1987-08-19 1987-08-19 Loop back control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20590487A JPS6449344A (en) 1987-08-19 1987-08-19 Loop back control system

Publications (1)

Publication Number Publication Date
JPS6449344A true JPS6449344A (en) 1989-02-23

Family

ID=16514676

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20590487A Pending JPS6449344A (en) 1987-08-19 1987-08-19 Loop back control system

Country Status (1)

Country Link
JP (1) JPS6449344A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010011001A (en) * 2008-06-26 2010-01-14 Fujitsu Telecom Networks Ltd Data transmission system and test control method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010011001A (en) * 2008-06-26 2010-01-14 Fujitsu Telecom Networks Ltd Data transmission system and test control method

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