JPS6449355A - Carrier reproducing circuit - Google Patents

Carrier reproducing circuit

Info

Publication number
JPS6449355A
JPS6449355A JP62205760A JP20576087A JPS6449355A JP S6449355 A JPS6449355 A JP S6449355A JP 62205760 A JP62205760 A JP 62205760A JP 20576087 A JP20576087 A JP 20576087A JP S6449355 A JPS6449355 A JP S6449355A
Authority
JP
Japan
Prior art keywords
synchronization
circuit
error correcting
symbol
data demodulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62205760A
Other languages
Japanese (ja)
Inventor
Seiya Inoue
Hitoshi Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP62205760A priority Critical patent/JPS6449355A/en
Publication of JPS6449355A publication Critical patent/JPS6449355A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To determine without fail whether or not a data demodulator is in a synchronizing condition and to prevent the occurrence of a pseudo synchronizing condition by providing an error correcting circuit in a carrier reproducing circuit with the data demodulator, and deciding the synchronization at the time of the carrier reproduction based on symbol synchronization deciding information. CONSTITUTION:An error correcting circuit 17 and an AND circuit 18 is provided. In the carrier reproducing circuit of such a constitution, when a data demodulator 1 is in the pseudo synchronization condition, data to be sent to the error correcting circuit 17 do not obey the rule of an error correcting symbol. Thus, a symbol synchronization in the error correcting circuit 17 is not established. Consequently, by obtaining the AND of the symbol synchronization information from the error correcting circuit 17 and the synchronization information of the data demodulator 1 with the AND circuit 18, it can be judged without fail whether or not the synchronization is attained, and the pseudo synchronization can be avoided.
JP62205760A 1987-08-19 1987-08-19 Carrier reproducing circuit Pending JPS6449355A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62205760A JPS6449355A (en) 1987-08-19 1987-08-19 Carrier reproducing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62205760A JPS6449355A (en) 1987-08-19 1987-08-19 Carrier reproducing circuit

Publications (1)

Publication Number Publication Date
JPS6449355A true JPS6449355A (en) 1989-02-23

Family

ID=16512212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62205760A Pending JPS6449355A (en) 1987-08-19 1987-08-19 Carrier reproducing circuit

Country Status (1)

Country Link
JP (1) JPS6449355A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08265384A (en) * 1995-03-22 1996-10-11 Nec Corp Demodulator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08265384A (en) * 1995-03-22 1996-10-11 Nec Corp Demodulator

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