JPS645242A - Bit scramble circuit - Google Patents

Bit scramble circuit

Info

Publication number
JPS645242A
JPS645242A JP62161788A JP16178887A JPS645242A JP S645242 A JPS645242 A JP S645242A JP 62161788 A JP62161788 A JP 62161788A JP 16178887 A JP16178887 A JP 16178887A JP S645242 A JPS645242 A JP S645242A
Authority
JP
Japan
Prior art keywords
circuit
scramble
bit
signal
scramble control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62161788A
Other languages
Japanese (ja)
Inventor
Tetsuo Kuchiki
Katsuichi Ogasawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP62161788A priority Critical patent/JPS645242A/en
Publication of JPS645242A publication Critical patent/JPS645242A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form a scramble and a descramble circuit as very simple and inexpensive stable circuits by ciphering a control signal for scramble control and sending the result, decoding the cryptographic signal and converting the bit arrangement. CONSTITUTION:After a digital video processing is applied by a signal processing circuit 3, a bit scramble circuit 4 applies scrambling to a bit by using scramble control information of a scramble control circuit 5. On the other hand, the output of the scramble control circuit 5 is ciphered through a ciphering circuit 7 and the result is sent. At the receiver side, the information given from a scramble control information input terminal 11 is inputted to a decoding circuit 14 and converted into the original bit string by controlling the bit descrambling circuit 13. Thus, the scramble and the descramble circuits are formed to be very simple, inexpensive and stable circuits and sufficient scrambling is applied to the original signal.
JP62161788A 1987-06-29 1987-06-29 Bit scramble circuit Pending JPS645242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62161788A JPS645242A (en) 1987-06-29 1987-06-29 Bit scramble circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62161788A JPS645242A (en) 1987-06-29 1987-06-29 Bit scramble circuit

Publications (1)

Publication Number Publication Date
JPS645242A true JPS645242A (en) 1989-01-10

Family

ID=15741918

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62161788A Pending JPS645242A (en) 1987-06-29 1987-06-29 Bit scramble circuit

Country Status (1)

Country Link
JP (1) JPS645242A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998003955A1 (en) * 1996-07-19 1998-01-29 Takaaki Nakamura Digital data shuffling/deshuffling system
JP2008236777A (en) * 1998-10-07 2008-10-02 Sony Corp Decoding device, decoding method, recording medium, and data processing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998003955A1 (en) * 1996-07-19 1998-01-29 Takaaki Nakamura Digital data shuffling/deshuffling system
JP2008236777A (en) * 1998-10-07 2008-10-02 Sony Corp Decoding device, decoding method, recording medium, and data processing device

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